AURA SOM/AURA Hardware/Peripherals/SPI
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Peripheral SPI[edit | edit source]
A SPI bus is a synchronous serial communication interface used in embedded systems. It is typically used to perform short-distance communications between microcontrollers and peripheral devices.
The SPI interface available on AURA is based on i.MX93 SoC. The chip includes eight instances of LPSPI Modules:
- LPSPI1 and LPSPI2 are in Low Power Real Time Domain
- LPSPI[3..8] are in Application Flex Domain
- SPI1 and SPI2 are only supported in Master Mode, not Slave Mode.
Description[edit | edit source]
The SPI port supports the following standards and features:
- FIFO register access supported by DMA transmit and receive requests
- Continues operating in Stop mode, if configured to do so and an appropriate clock is available
- 32-bit word size
- Configurable clock polarity and phase
- Master mode—supports 2 peripheral chip selects and Slave mode
- 8-word transmit, receive and command FIFO
- Flexible timing parameters in Master mode, including SCK frequency and duty cycle, and delays between PCS and SCK edges
- Continuous transfer option to keep PCS asserted across multiple frames
- Full-duplex transfers support 1-bit transmit and receive on each clock edge and Half-duplex transfers support
Pin mapping[edit | edit source]
The Pin mapping is described in the Pinout table section
