Difference between revisions of "DESK-XZ7-L/Development/Creating and building the Vivado project"

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__FORCETOC__
 
__FORCETOC__
 
<section begin=Body/>
 
<section begin=Body/>
−
 
−
{{ImportantMessage|text=Vivado installation path, in this documentation, is the <code>/opt</code> directory. If you have chosen a different one, set it properly. The commands reported here below have been used on a native server running Ubuntu 20.04.}}
 
−
 
  
 
== Creating and building the Vivado project ==
 
== Creating and building the Vivado project ==
 
The Vivado repository allows to:
 
The Vivado repository allows to:
 
* track hardware/fpga related sources/configuration
 
* track hardware/fpga related sources/configuration
−
* reproduce hardware design output (FPGA bitstream, XSA) using TCL scripts
+
* reproduce hardware design output (FPGA bitstream, XSA) using TCL scripts. Development kit TCL scripts supported are as follow:
−
 
 
−
Development kit TCL scripts supported are the following one:
 
  
 
{| class="wikitable"
 
{| class="wikitable"
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|}
 
|}
  
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As an example, to reproduce the build for the ''Bora'' platform, here below are the steps:
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Take ''Bora'' platform for example, to reproduce the build, user just need to:
 
* clone the repository:
 
* clone the repository:
 
<syntaxhighlight lang="bash">
 
<syntaxhighlight lang="bash">
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</syntaxhighlight>
 
</syntaxhighlight>
  
−
or clone the Vivado repository when you clone Petalinux repository
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or you can clone Vivado repository when you clone Petalinux repository
  
 
<syntaxhighlight lang="bash">
 
<syntaxhighlight lang="bash">
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</syntaxhighlight>
 
</syntaxhighlight>
  
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* (only once as first tools setup) copy ''Bora'' hardware definition into Vivado installation path:
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* (only once as first tools setup) copy ''Bora'' hardware definition into Vivado installation.:
 
<syntaxhighlight lang="bash">
 
<syntaxhighlight lang="bash">
−
cp -r boards/ <vivado directory installation>/Xilinx/2021.2/Vivado/2021.2/data/
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cp -r boards/ /opt/Xilinx/2021.2/Vivado/2021.2/data/
 
</syntaxhighlight>
 
</syntaxhighlight>
−
* lunch Vivado Design Suite with the following commands and parameters:
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* lunch Vivado Design Suite with the following command:
 
<syntaxhighlight lang="bash">
 
<syntaxhighlight lang="bash">
−
source <vivado directory installation>/Xilinx/2021.2/Vivado/2021.2/settings64.sh
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source /opt/Xilinx/2021.2/Vivado/2021.2/settings64.sh
 
vivado -mode tcl -source scripts/recreate_prj_bora_BASE.tcl -notrace -tclargs "gen_bitstream"
 
vivado -mode tcl -source scripts/recreate_prj_bora_BASE.tcl -notrace -tclargs "gen_bitstream"
 
</syntaxhighlight>
 
</syntaxhighlight>
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* at the end of the bitstream build process, the script automatically exports the Xilinx Support Archive ('''XSA''') hardware design
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* at the end of bitstream build process, the script automatically exports hardware
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** the Vivado project <code>vivado/bora.xpr</code> is ready for customization through the Vivado GUI
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** The Vivado project ready for customization through Vivado GUI is available into <code>vivado/bora.xpr</code>
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** the bitstream files are
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** The bitstream file is now present in
 
*** <code>vivado/bora.runs/impl_1/bora_wrapper.bit</code>
 
*** <code>vivado/bora.runs/impl_1/bora_wrapper.bit</code>
 
*** <code>vivado/bora.runs/impl_1/bora_wrapper.bin</code>
 
*** <code>vivado/bora.runs/impl_1/bora_wrapper.bin</code>
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** the hardware design file <code>vivado/bora.xsa</code> is ready for the import into Petalinux
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** The hardware export, ready for import into Petalinux, is available in <code>vivado/bora.xsa</code>
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+
<section end=Body/>
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=== CAN0 and UART0 routing example project ===
 
−
 
 
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The following pictures show a simple PL design used to route PS' CAN0 and UART0 signals through EMIO.
 
−
 
 
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[[File:Belk-default-vivado-project.png|thumb|center|400px|Block diagram of BORA example project]]
 
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[[File:Belk-borax-default-vivado-project.png|thumb|center|400px|Block diagram of BORA Xpress example project]]
 
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[[File:Boralite-default-vivado-project.png|thumb|center|400px|Block diagram of BORA Lite example project]]
 
  
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<section end=Body/>
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----
  
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[[Category:BORA]] [[Category:BORA Xpress]][[Category:BORA Lite]]
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[[Category:BORA]]

Revision as of 14:05, 22 January 2024

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History
Issue Date Notes
2022/11/15 DESK-XZ7-L-1.0.0-rc1 release
2024/01/12 DESK-XZ7-L-1.0.1 release



Creating and building the Vivado project[edit | edit source]

The Vivado repository allows to:

  • track hardware/fpga related sources/configuration
  • reproduce hardware design output (FPGA bitstream, XSA) using TCL scripts. Development kit TCL scripts supported are as follow:
Script Boot
recreate_prj_bora.tcl uSD and QSPI-NOR
recreate_prj_borax_BASE.tcl uSD and QSPI-NOR
recreate_prj_boralite_BASE.tcl uSD and QSPI-NOR
recreate_prj_boralite_NAND.tcl uSD and NAND

Take Bora platform for example, to reproduce the build, user just need to:

  • clone the repository:
git clone git@git.dave.eu:desk-xz-l/vivado.git -b desk-xz7-l-1.0.1
cd vivado

or you can clone Vivado repository when you clone Petalinux repository 

git clone --recursive git@git.dave.eu:desk-xz-l/petalinux.git -b desk-xz7-l-1.0.1
cd petalinux/vivado
  • (only once as first tools setup) copy Bora hardware definition into Vivado installation.:
cp -r boards/ /opt/Xilinx/2021.2/Vivado/2021.2/data/
  • lunch Vivado Design Suite with the following command:
source /opt/Xilinx/2021.2/Vivado/2021.2/settings64.sh
vivado -mode tcl -source scripts/recreate_prj_bora_BASE.tcl -notrace -tclargs "gen_bitstream"
  • at the end of bitstream build process, the script automatically exports hardware
    • The Vivado project ready for customization through Vivado GUI is available into vivado/bora.xpr
    • The bitstream file is now present in
      • vivado/bora.runs/impl_1/bora_wrapper.bit
      • vivado/bora.runs/impl_1/bora_wrapper.bin
    • The hardware export, ready for import into Petalinux, is available in vivado/bora.xsa


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