Difference between revisions of "BORA Lite SOM/BORA Lite Hardware/Power and Reset/System boot"

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{{#lst:System_boot_and_recovery_via_microSD_card_(BELK/BXELK)|BELK}}
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|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|New documentation layout
 
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__FORCETOC__
 
<section begin=Body/>
 
 
 
== System boot ==
 
 
 
The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM core to begin execution starting from the on-chip boot ROM.
 
The boot process is multi-stage and minimally includes the Boot ROM and the first-stage boot loader (FSBL). The Zynq-7000 AP SoC includes a factory-programmed Boot ROM that is not useraccessible.
 
The boot ROM:
 
* determines whether the boot is secure or non-secure
 
* performs some initialization of the system and cleanups
 
* reads the mode pins to determine the primary boot device
 
* once it is satisfied, it executes the FSBL
 
 
 
After a system reset, the system automatically sequences to initialize the system and process the first stage boot loader from the selected external boot device.
 
The process enables the user to configure the AP SoC platform as needed, including the PS and the PL.
 
Optionally, the JTAG interface can be enabled to give the design engineer access to the PS and the PL for test and debug purposes.
 
 
 
=== Boot options ===
 
 
 
The boot ROM supports configuration from four different slave interfaces:
 
* Quad-SPI
 
* NAND
 
* NOR flash (not available on [[BORA Lite SOM | BORA Lite]])
 
* SD card
 
 
 
Boot mode is selectable via five mode pins (BOOT_MODE[4:0]), and two voltage mode signals, (VMODE[1:0]). The BOOT_MODE pins are MIO[6:2] and the VMODE pins are MIO[8:7]. The pins are used as follows:
 
 
 
{|class="wikitable" style="text-align: center;"
 
|-
 
!Function
 
!Boot signals
 
!Available options
 
|-
 
| JTAG mode || BOOT_MODE[3]<br>MIO[2]|| 0: Cascaded JTAG<br>1: Independent JTAG
 
|-
 
| Boot mode || BOOT_MODE[0-2-1]<br>MIO[5:3] || 000: JTAG<br>010: NAND<br>100: Quad-SPI<br>110: SD card
 
|-
 
| PLLs enable || BOOT_MODE[4]<br>MIO[6] || 0: PLL used<br>1: PLL bypassed
 
|-
 
| MIO Bank 0 Voltage || VMODE[0]<br>MIO[7] || 0: 2.5 V, 3.3 V<br>1: 1.8 V
 
|-
 
|MIO Bank 0 Voltage || VMODE[1]<br>MIO[8] || 0: 2.5 V, 3.3 V<br>1: 1.8 V
 
|-
 
|}
 
 
 
In order to fully understand how boot works on BORA Lite platform, please refer to chapter 6 ("Boot and configuration") of the Zynq7000 Technical Reference Manual.
 
 
 
=== Default boot configuration ===
 
 
 
Default configuration for BORA Lite module is:
 
* Mode[0..3] = 1000: Quad-SPI mode
 
* Mode[4] = 0: PLL not bypassed
 
* VCFG[0] = 0: 2.5V, 3.3V operations for bank 0
 
* VCFG[1] = 1: 1.8 operations for bank 1
 
 
 
Assuming that:
 
* default configuration is not changed
 
* there's a valid boot code programmed in SPI flash memory the actual boot sequence performed by ARM core will be:
 
# Bootrom is executed from internal ROM code memory
 
# FSBL is copied from on-board NOR flash memory connected to SPI0 port to on-chip SRAM by bootrom
 
# FSBL is executed from on-chip SRAM
 
# U-Boot bootloader (2nd stage) is copied by FSBL from NOR flash memory connected to Quad-SPI port to SDRAM
 
# U-boot (2nd stage) is executed from SDRAM
 
 
 
If no boot code is available in SPI NOR flash, the bootrom tries JTAG peripheral booting.
 
 
 
=== Boot sequence customization ===
 
 
 
BOOT_MODE[4:0] are routed to the J1 connector, enabling for the customization of the boot sequence through a simple resistor network that can be implemented on carrier board hosting BORA Lite module.
 
 
 
{|class="wikitable" style="text-align: center;"
 
|-
 
!Mode signal
 
!J1 pin
 
!Pin name
 
|-
 
| BOOT_MODE[4] || J1.54 || SPI0_SCLK/MODE4/NAND_IO1
 
|-
 
| BOOT_MODE[3] || J1.46 || SPI0_DQ0/MODE3/NAND_ALE
 
|-
 
| BOOT_MODE[2] || J1.50 || SPI0_DQ2/MODE2/NAND_IO2
 
|-
 
| BOOT_MODE[1] || J1.48 || SPI0_DQ1/MODE1/NAND_WE
 
|-
 
| BOOT_MODE[0] || J1.52 || SPI0_DQ3/MODE0/NAND_IO0
 
|}
 
 
 
----
 
 
 
[[Category:BORA Lite]]
 

Revision as of 09:44, 28 October 2021

System boot and recovery via microSD card[edit | edit source]

BELK provides a bootable microSD that can be used not only to quickly start the system, but also as a recovery method in case the primary boot device (eg. QSPI NOR flash) gets erased or corrupted. The following sections describe how to create a bootable SD card and how to configure the system for booting from SD. This article, for example, shows how to make use of such a card to restore the U-Boot image onto the NOR flash.


200px-Emblem-important.svg.png

It is worth remembering that the bootable microSD card described in this article is not configured to perform a full boot sequence, including the operating system bootstrap. The bootable microSD card delivered along with the kit is set up to do a full bootstrap sequence, instead. For more details, please refer to this section.

How to create a bootable microSD card[edit | edit source]

BELK <= 3.0.2 / BXELK <= 1.0.1[edit | edit source]

This section describes how to create a new bootable microSD card from scratch for BELK <= 3.0.2 and BXELK <= 1.0.1. The following components must be available:

  • FSBL built with Vivado 2014.4 as described here
  • U-boot built in elf format, as described in here
  • FPGA bitstream (optional).

The procedure is the following:

  • from the Vivado 2014.4 SDK, apply the required patches to the main.c project file.This step can be done in two ways:
    • manually, directly modifying the main.c file adding the following code snippets:
----CUT----
	/*
	 * Unlock SLCR for SLCR register write
	 */
	SlcrUnlock();

+	*((u32 *)0xF8000830) = 0x003F003F;
+	*((u32 *)0xF8000834) = 0x003F003F;

	/* If Performance measurement is required 
	 * then read the Global Timer value , Please note that the
----CUT----

----CUT----
	/*
	 * Read bootmode register
	 */
	BootModeRegister = Xil_In32(BOOT_MODE_REG);
	BootModeRegister &= BOOT_MODES_MASK;

+	// always init QSPI
+	InitQspi();
	
	/*
	 * QSPI BOOT MODE
	 */
#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
----CUT----
    • automatically, using the Apply Patch function and selecting the belk-sd-boot.patch file provided with the BELK (please refer to the following images):
Automatic patch applying (1/3)
Automatic patch applying (2/3)
Automatic patch applying (3/3)
  • once the patch is applied, rebuild the FSBL project
  • from the Xilinx Tools menu, select Create Zynq Boot Image
  • select Create New BIF file and insert path and name of the .bif file
  • in the Boot image partitions section, click on Add to browse and add the following files:
    • FSBL in .elf format, with bootloader as partition type
    • (optional) FPGA bitstream in .bit format, with partition type datafile
    • U-boot binary with .elf extension, with partition type datafile
  • in the Output path section, browse and select the path where saving the boot.bin file
  • on a PC, format the microSD card creating a FAT32 partition
  • copy the boot.bin file to the microSD card FAT32 partition.

BELK-4.0.0 / BXELK-2.0.0[edit | edit source]

This section describes how to create a new bootable microSD card from scratch for BELK-4.0.0 and BXELK-2.0.0. The following components must be available:

  • U-boot SPL and U-boot second stage built as described in here
  • FPGA bitstream (optional).

The procedure is the following:

  • on a PC, format the microSD card creating a FAT32 partition
  • copy the following files to the microSD card FAT32 partition:
    • U-boot SPL: boot.bin
    • U-boot second stage: u-boot.img
    • Fpga bitstream .bit (optional): fpga.bit

How to configure the system for microSD boot[edit | edit source]

For BORA / BORA Evaluation kit systems please refer to this link.

For BORA Xpress/ BORA xpress Evaluation kit systems please refer to this link.

For BORA Lite Evaluation kit systems please refer to this link.


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In case the microSD card provided along with the kit is used, the Programmable Logic is automatically programmed with the example design during the boot process.