Bureaucrats, dave_user, Administrators
4,650
edits
Changes
→J1 even pins (2 to 140)
| J1.118||DGND||DGND||-||-||-||-||Digital ground
|-
| J1.120||SPI0_CS0n||CPU.PS_MIO1_500<br>NOR flash||CPU.A22||Bank 500||I/O||3.3V||
|-
| J1.122||NAND_CS0/SPI0_CS1||CPU.PS_MIO0_500<br>NAND flash||CPU.G17||Bank 500||I/O||3.3V||10kOhm pull-up
|-
| J1.124||NAND_IO3||CPU.PS_MIO13_500<br>NAND flash||CPU.A17||Bank 500||I/O||3.3V||
|-
| J1.126||NAND_IO4||CPU.PS_MIO9_500<br>NAND flash||CPU.C19||Bank 500||I/O||3.3V||
|-
| J1.128||NAND_IO5||CPU.PS_MIO10_500<br>NAND flash||CPU.G16||Bank 500||I/O||3.3V||
|-
| J1.130||DGND||DGND||-||-||-||-||Digital ground
|-
| J1.132||NAND_IO6||CPU.PS_MIO11_500<br>NAND flash||CPU.B19||Bank 500||I/O||3.3V||
|-
| J1.134||NAND_IO7||CPU.PS_MIO12_500<br>NAND flash||CPU.C18||Bank 500||I/O||3.3V||
|-
| J1.136||NAND_RD_B/VCFG1||CPU.PS_MIO8_500<br>NAND flash||CPU.E18||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
|-
| J1.138||NAND_CLE/VCFG0||CPU.PS_MIO7_500<br>NAND flash||CPU.D18||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
|-
| J1.140||DGND||DGND||-||-||-||-||Digital ground
