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→J1 even pins (2 to 140)
==J1 even pins (2 to 140)==
{| class="wikitable" {| {{table}}
| align="center" style="background:#f0f0f0;"|'''Pin'''
| align="center" style="background:#f0f0f0;"|'''Pin Name'''
| align="center" style="background:#f0f0f0;"|'''Internal Connections'''
| align="center" style="background:#f0f0f0;"|'''Ball/pin #'''
| align="center" style="background:#f0f0f0;"|'''Supply Group'''
| align="center" style="background:#f0f0f0;"|'''Type'''
| align="center" style="background:#f0f0f0;"|'''Voltage'''
| align="center" style="background:#f0f0f0;"|'''Note'''
|-
| J1.2||VDDIO_BANK35||||||||S||||
|-
| J1.4||DGND||DGND||-||-||-||-||Digital ground
|-
| J1.6||IO_L24P_T3_AD15P_35||FPGA.IO_L24P_T3_AD15P_35||H1||Bank 35||I/O||User defined||
|-
| J1.8||IO_L24N_T3_AD15N_35||FPGA.IO_L24N_T3_AD15N_35||G1||Bank 35||I/O||User defined||
|-
| J1.10||IO_L22P_T3_AD7P_35||FPGA.IO_L22P_T3_AD7P_35||G3||Bank 35||I/O||User defined||
|-
| J1.12||IO_L22N_T3_AD7N_35||FPGA.IO_L22N_T3_AD7N_35||G2||Bank 35||I/O||User defined||
|-
| J1.14||DGND||DGND||-||-||-||-||Digital ground
|-
| J1.16||IO_L20P_T3_AD6P_35||FPGA.IO_L20P_T3_AD6P_35||G4||Bank 35||I/O||User defined||
|-
| J1.18||IO_L20N_T3_AD6N_35||FPGA.IO_L20N_T3_AD6N_35||F4||Bank 35||I/O||User defined||
|-
| J1.20||IO_L18P_T2_AD13P_35||FPGA.IO_L20N_T3_AD6N_35||B2||Bank 35||I/O||User defined||
|-
| J1.22||IO_L18N_T2_AD13N_35||FPGA.IO_L18N_T2_AD13N_35||B1||Bank 35||I/O||User defined||
|-
| J1.24||DGND||DGND||-||-||-||-||Digital ground
|-
| J1.26||IO_L16P_T2_35||FPGA.IO_L16P_T2_35||D1||Bank 35||I/O||User defined||
|-
| J1.28||IO_L16N_T2_35||FPGA.IO_L16N_T2_35||C1||Bank 35||I/O||User defined||
|-
| J1.30||DGND||DGND||-||-||-||-||Digital ground
|-
| J1.32||IO_L14P_T2_AD4P_SRCC_35||FPGA.IO_L14P_T2_AD4P_SRCC_35||D3||Bank 35||I/O||User defined||
|-
| J1.34||IO_L14N_T2_AD4N_SRCC_35||FPGA.IO_L14N_T2_AD4N_SRCC_35||C3||Bank 35||I/O||User defined||
|-
| J1.36||IO_L12P_T1_MRCC_35||FPGA.IO_L12P_T1_MRCC_35||D5||Bank 35||I/O||User defined||
|-
| J1.38||DGND||DGND||-||-||-||-||Digital ground
|-
| J1.40||IO_L12N_T1_MRCC_35||FPGA.IO_L12N_T1_MRCC_35||C4||Bank 35||I/O||User defined||
|-
| J1.42||IO_L10P_T1_AD11P_35||FPGA.IO_L10P_T1_AD11P_35||A5||Bank 35||I/O||User defined||
|-
| J1.44||IO_L10N_T1_AD11N_35||FPGA.IO_L10N_T1_AD11N_35||A4||Bank 35||I/O||User defined||
|-
| J1.46||IO_L8P_T1_AD10P_35||FPGA.IO_L8P_T1_AD10P_35||B7||Bank 35||I/O||User defined||
|-
| J1.48||DGND||DGND||-||-||-||-||Digital ground
|-
| J1.50||IO_L8N_T1_AD10N_35||FPGA.IO_L8N_T1_AD10N_35||B6||Bank 35||I/O||User defined||
|-
| J1.52||IO_L6P_T0_35||FPGA.IO_L6P_T0_35||G6||Bank 35||I/O||User defined||
|-
| J1.54||IO_L6N_T0_VREF_35||FPGA.IO_L6N_T0_VREF_35||F6||Bank 35||I/O||User defined||
|-
| J1.56||IO_L4P_T0_35||FPGA.IO_L4P_T0_35||G8||Bank 35||I/O||User defined||
|-
| J1.58||IO_L4N_T0_35||FPGA.IO_L4N_T0_35||G7||Bank 35||I/O||User defined||
|-
| J1.60||DGND||DGND||-||-||-||-||Digital ground
|-
| J1.62||IO_L2P_T0_AD8P_35||FPGA.IO_L2P_T0_AD8P_35||D7||Bank 35||I/O||User defined||
|-
| J1.64||IO_L2N_T0_AD8N_35||FPGA.IO_L2N_T0_AD8N_35||D6||Bank 35||I/O||User defined||
|-
| J1.66||VDDIO_BANK35||||||||S||||
|-
| J1.68||VDDIO_BANK35||||||||S||||
|-
| J1.70||XADC_AGND||||||||G||||XADC analog ground (internally connected to DGND)
|-
| J1.72||XADC_AGND||||||||G||||XADC analog ground (internally connected to DGND)
|-
| J1.74||IO_0_VRN_35||FPGA.IO_0_35/IO_0_VRN_35||H6||Bank 35||I/O||User defined||Optional on-board pull-up
|-
| J1.76||RFU||-||-||-||-||-||Reserved fo future use. Must be left floating.
|-
| J1.78||RFU||-||-||-||-||-||Reserved fo future use. Must be left floating.
|-
| J1.80||PS_MIO49_501||CPU.PS_MIO49_501||C9||Bank 501||I/O||1.8V||
|-
| J1.82||PS_MIO48_501||CPU.PS_MIO48_501||D12||Bank 501||I/O||1.8V||
|-
| J1.84||PS_MIO47_501||CPU.PS_MIO47_501||B13||Bank 501||I/O||1.8V||10kOhm pull-up
TBD
|-
| J1.86||DGND||DGND||-||-||-||-||Digital ground
|-
| J1.88||PS_MIO46_501||CPU.PS_MIO46_501||D11||Bank 501||I/O||1.8V||10kOhm pull-up
TBD
|-
| J1.90||ETH_INTn||||||||||||Can be optionally connected to Ethernet PHY's INT_N / PME_N2
|-
| J1.92||DGND||DGND||-||-||-||-||Digital ground
|-
| J1.94||ETH_TXRX3_M||LAN.TXRXM_D||11||||D||||
|-
| J1.96||ETH_TXRX3_P||LAN.TXRXP_D||10||||D||||
|-
| J1.98||DGND||DGND||-||-||-||-||Digital ground
|-
| J1.100||ETH_TXRX2_M||||||||||||
|-
| J1.102||ETH_TXRX2_P||||||||||||
|-
| J1.104||DGND||DGND||-||-||-||-||Digital ground
|-
| J1.106||CLK125_NDO||LAN.CLK125_NDO||41||||O||1.8V||10kOhm pull-up
|-
| J1.108||RFU||-||-||-||-||-||Reserved fo future use. Must be left floating.
|-
| J1.110||RFU||-||-||-||-||-||Reserved fo future use. Must be left floating.
|-
| J1.112||DGND||DGND||-||-||-||-||Digital ground
|-
| J1.114||USBP1||USB.DP||6||||D||||
|-
| J1.116||USBM1||USB.DM||5||||D||||
|-
| J1.118||DGND||DGND||-||-||-||-||Digital ground
|-
| J1.120||SPI0_CS0n||CPU.PS_MIO1_500
NOR flash||CPU.A22
||Bank 500||I/O||3.3V||
|-
| J1.122||NAND_CS0/SPI0_CS1||CPU.PS_MIO0_500
NAND flash||CPU.G17||Bank 500||I/O||3.3V||10kOhm pull-up
|-
| J1.124||NAND_IO3||CPU.PS_MIO13_500
NAND flash||CPU.A17||Bank 500||I/O||3.3V||
|-
| J1.126||NAND_IO4||CPU.PS_MIO9_500
NAND flash||CPU.C19||Bank 500||I/O||3.3V||
|-
| J1.128||NAND_IO5||CPU.PS_MIO10_500
NAND flash||CPU.G16||Bank 500||I/O||3.3V||
|-
| J1.130||DGND||DGND||-||-||-||-||Digital ground
|-
| J1.132||NAND_IO6||CPU.PS_MIO11_500
NAND flash||CPU.B19||Bank 500||I/O||3.3V||
|-
| J1.134||NAND_IO7||CPU.PS_MIO12_500
NAND flash||CPU.C18||Bank 500||I/O||3.3V||
|-
| J1.136||NAND_RD_B/VCFG1||CPU.PS_MIO8_500
NAND flash||CPU.E18||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
|-
| J1.138||NAND_CLE/VCFG0||CPU.PS_MIO7_500
NAND flash||CPU.D18||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
|-
| J1.140||DGND||DGND||-||-||-||-||Digital ground
|}
==J2 odd pins (1 to 139)==
