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→J2 odd pins (1 to 139)
==J2 odd pins (1 to 139)==
{| class="wikitable" {| {{table}}
| align="center" style="background:#f0f0f0;"|'''Pin'''
| align="center" style="background:#f0f0f0;"|'''Pin Name'''
| align="center" style="background:#f0f0f0;"|'''Internal Connections'''
| align="center" style="background:#f0f0f0;"|'''Ball/pin #'''
| align="center" style="background:#f0f0f0;"|'''Supply Group'''
| align="center" style="background:#f0f0f0;"|'''Type'''
| align="center" style="background:#f0f0f0;"|'''Voltage'''
| align="center" style="background:#f0f0f0;"|'''Note'''
|-
| J2.1||DGND||DGND||-||-||G||-||Digital ground
|-
| J2.3||DGND||DGND||-||-||G||-||Digital ground
|-
| J2.5||IO_L8P_T1_34||FPGA.IO_L8P_T1_34||J2||Bank 34||I/O||User defined||
|-
| J2.7||IO_L8N_T1_34||FPGA.IO_L8N_T1_34||J1||Bank 34||I/O||User defined||
|-
| J2.9||IO_L6P_T0_34||FPGA.IO_L6P_T0_34||M8||Bank 34||I/O||User defined||CAN_RX
|-
| J2.11||IO_L6N_T0_VREF_34||FPGA.IO_L6N_T0_VREF_34||M7||Bank 34||I/O||User defined||
|-
| J2.13||DGND||DGND||-||-||G||-||Digital ground
|-
| J2.15||IO_L3P_T0_DQS_PUDC_B_34||FPGA.IO_L3P_T0_DQS_PUDC_B_34||K7||Bank 34||I/O||User defined||Internally connected to VDDIO_BANK34 via 10K resistor
|-
| J2.17||IO_L3N_T0_DQS_34||FPGA.IO_L3N_T0_DQS_34||L7||Bank 34||I/O||User defined||
|-
| J2.19||IO_L2P_T0_34||FPGA.IO_L2P_T0_34||J7||Bank 34||I/O||User defined||
|-
| J2.21||IO_L2N_T0_34||FPGA.IO_L2N_T0_34||J6||Bank 34||I/O||User defined||
|-
| J2.23||DGND||DGND||-||-||G||-||Digital ground
|-
| J2.25||IO_L22P_T3_34||FPGA.IO_L22P_T3_34||M4||Bank 34||I/O||User defined||
|-
| J2.27||IO_L22N_T3_34||FPGA.IO_L22N_T3_34||M3||Bank 34||I/O||User defined||
|-
| J2.29||IO_L21P_T3_DQS_34||FPGA.IO_L21P_T3_DQS_34||N4||Bank 34||I/O||User defined||
|-
| J2.31||IO_L21N_T3_DQS_34||FPGA.IO_L21N_T3_DQS_34||N3||Bank 34||I/O||User defined||
|-
| J2.33||DGND||DGND||-||-||G||-||Digital ground
|-
| J2.35||IO_L19P_T3_34||FPGA.IO_L19P_T3_34||N6||Bank 34||I/O||User defined||CAN_TX
|-
| J2.37||IO_L19N_T3_VREF_34||FPGA.IO_L19N_T3_VREF_34||N5||Bank 34||I/O||User defined||
|-
| J2.39||IO_L18P_T2_34||FPGA.IO_L18P_T2_34||P3||Bank 34||I/O||User defined||
|-
| J2.41||IO_L18N_T2_34||FPGA.IO_L18N_T2_34||P2||Bank 34||I/O||User defined||
|-
| J2.43||DGND||DGND||-||-||G||-||Digital ground
|-
| J2.45||IO_L15P_T2_DQS_34||FPGA.IO_L15P_T2_DQS_34||M2||Bank 34||I/O||User defined||
|-
| J2.47||IO_L15N_T2_DQS_34||FPGA.IO_L15N_T2_DQS_34||M1||Bank 34||I/O||User defined||
|-
| J2.49||DGND||DGND||-||-||G||-||Digital ground
|-
| J2.51||IO_L13P_T1_MRCC_34||FPGA.IO_L13P_T1_MRCC_34||T2||Bank 34||I/O||User defined||
|-
| J2.53||IO_L13N_T1_MRCC_34||FPGA.IO_L13N_T1_MRCC_34||T1||Bank 34||I/O||User defined||
|-
| J2.55||DGND||DGND||-||-||G||-||Digital ground
|-
| J2.57||IO_L11P_T1_SRCC_34||FPGA.IO_L11P_T1_SRCC_34||K4||Bank 34||I/O||User defined||
|-
| J2.59||IO_L11N_T1_SRCC_34||FPGA.IO_L11N_T1_SRCC_34||K3||Bank 34||I/O||User defined||
|-
| J2.61||DGND||DGND||-||-||G||-||Digital ground
|-
| J2.63||IO_L10P_T1_34||FPGA.IO_L10P_T1_34||L2||Bank 34||I/O||User defined||
|-
| J2.65||IO_L10N_T1_34||FPGA.IO_L10N_T1_34||L1||Bank 34||I/O||User defined||
|-
| J2.67||IO_25_VRP_34||FPGA.IO_25_VRP_34||R8||Bank 34||I/O||User defined||Optional Internal Termination resistors for DCI
|-
| J2.69||IO_0_VRN_34||FPGA.IO_0_VRN_34||H8||Bank 34||I/O||User defined||Optional Internal Termination resistors for DCI
|-
| J2.71||DGND||DGND||-||-||G||-||Digital ground
|-
| J2.73||RFU||-||-||-||-||-||Reserved for future use. Must be left floating.
|-
| J2.75||RFU||-||-||-||-||-||Reserved for future use. Must be left floating.
|-
| J2.77||RFU||-||-||-||-||-||Reserved for future use. Must be left floating.
|-
| J2.79||RFU||-||-||-||-||-||Reserved for future use. Must be left floating.
|-
| J2.81||RFU||-||-||-||-||-||Reserved for future use. Must be left floating.
|-
| J2.83||ETH0_PHY_RST||LAN.RESET_N||42||BANK 501||O||1.8V||Internally connected to DGND via 10K resistor
|-
| J2.85||USB0_PHY_RST||USB.RESETB||23||BANK 501||O||1.8V||Internally connected to DGND via 10K resistor
|-
| J2.87||CAN_3STn||LEVEL_SHIFTER.3ST#||6||BANK 34||I||User defined||"TBD
|-
| Internally connected to VDDIO_BANK34 via 10K resistor "
|-
| J2.89||EXT_VMON2_V1||-||-||-||-||||Reserved for future use. Must be left floating.
|-
| J2.91||EXT_VMON2_V2||-||-||-||-||||Reserved for future use. Must be left floating.
|-
| J2.93||RTC_32KHZ||RTC.32KHZ||1||3.3V||O||3.3V||
|-
| J2.95||RTC_RST||RTC.~RST||4||3.3V||I/O||3.3V||
|-
| J2.97||XADC_VN_R||FPGA.VN_0||L12||Bank 0||A||||
|-
| J2.99||XADC_VP_R||FPGA.VP_0||M11||Bank 0||A||||
|-
| J2.101||RFU||-||-||-||-||-||Reserved for future use. Must be left floating.
|-
| J2.103||CONN_SPI_RSTn||-||-||-||-||-||Reserved for future use. Must be left floating.
|-
| J2.105||CAN_L||CAN.CANL||6||-||D||-||
|-
| J2.107||CAN_H||CAN.CANH||7||-||D||-||
|-
| J2.109||DGND||DGND||-||-||G||-||Digital ground
|-
| J2.111||RTC_INT/SQW||RTC.RTC_INT/SQW||3||3.3V||I/O||3.3V||It can be left open if not used. When used, a proper pull-up resistor is required on the carrier board. For further details, please refer to the Maxim Integrated DS3232 datasheet.
|-
| J2.113||RTC_VBAT||RTC.VBAT||6||-||S||-||TBD
|-
| J2.115||VBAT||CPU.VCCBATT_0||G14||-||S||-||TBD
|-
| J2.117||DGND||DGND||-||-||G||-||Digital ground
|-
| J2.119||3.3VIN||3.3VIN||-||3.3VIN||S||+3.3V||SOM Power Supply
|-
| J2.121||3.3VIN||3.3VIN||-||3.3VIN||S||+3.3V||SOM Power Supply
|-
| J2.123||3.3VIN||3.3VIN||-||3.3VIN||S||+3.3V||SOM Power Supply
|-
| J2.125||DGND||DGND||-||-||G||-||Digital ground
|-
| J2.127||3.3VIN||3.3VIN||-||3.3VIN||S||+3.3V||SOM Power Supply
|-
| J2.129||3.3VIN||3.3VIN||-||3.3VIN||S||+3.3V||SOM Power Supply
|-
| J2.131||3.3VIN||3.3VIN||-||3.3VIN||S||+3.3V||SOM Power Supply
|-
| J2.133||3.3VIN||3.3VIN||-||3.3VIN||S||+3.3V||SOM Power Supply
|-
| J2.135||3.3VIN||3.3VIN||-||3.3VIN||S||+3.3V||SOM Power Supply
|-
| J2.137||3.3VIN||3.3VIN||-||3.3VIN||S||+3.3V||SOM Power Supply
|-
| J2.139||DGND||DGND||-||-||G||-||Digital ground
|}
==J2 even pins (2 to 140)==
