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→Design Overview
DDR3 SDRAM memory bank is composed by 2x 16-bit width chips resulting in a 32-bit combined width bank.
{| class="wikitable" |
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| CPU connection|| SDRAM bus||
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| Size min|| 512 MB||
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| Size max|| 1 GB||
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| Width|| 32 bit||
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| Speed|| 533 MHz||
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|+ align="bottom" style="caption-side: bottom" | Table: XC7-Z0x0 comparison
|}
== NOR flash bank ==
