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By default, this signal is connected to the on-board ETH Ethernet PHY reset inputas depicted in the above figure. This allows complete software control of PHY hardware reset sequence, even if FPGA is not programmedregardless of the PL status.

For example, this is how the reset signal is handled in the TBD (inserire riferimento al BSP): * U-Boot <code>board_init</code> software routine generates an a hardware reset pulse. This initializes the component to its default register values and then it will be correctly configured for properly working on BORA SOM, which are partly determined by the PHY's strapping pins.* Upon boot up, the Linux kernel will reset the ethernet PHY issuing issues a software reset via the BCMR register. If a hardware reset is requiredinstead, the <code>macb</code> kernel driver and/or the device tree properties have to be modified for including enabling this functionalityfeature.

By default, this signal is connected to the on-board USB PHY reset inputas depicted in the above figure. This allows complete software control of PHY hardware reset sequence, even if FPGA is not programmedregardless of the PL status.  * U-Boot <code>board_init</code> software routine generates an a hardware reset pulse. This initializes the component to its default register values and then it will be correctly configured for properly working on BORA SOM.  * Linux kernel does not issue any further hardware reset. If a hardware reset is requiredupon Linux boot up, the <code>phy-ulpi</code> kernel driver and/or the according device tree properties have to be modified for including enabling this functionalityfeature.

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