Bureaucrats, dave_user, Administrators
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By default, this signal is connected to on-board ETH PHY reset input. This allows complete software control of PHY reset sequence, even if FPGA is not programmed.
U-Boot <code>board_init</code> software routine generates an hardware reset pulse. This initializes the component to its default register values and then it wil will be correctly configured for properly working on BORA SOM.Linux kernel will reset the ethernet PHY issuing a software reset via BCMR register. If a hardware reset is required, the <code>macb</code> kernel driver and/or the device tree properties have to be modified for including this functionality.
==== PS_MIO50_501 ====
By default, this signal is connected to on-board USB PHY reset input. This allows complete software control of PHY reset sequence, even if FPGA is not programmed.
U-Boot <code>board_init</code> software routine generates an hardware reset pulse. This initializes the component to its default register values and then it wil will be correctly configured for properly working on BORA SOM. If a hardware reset is required, the <code>phy-ulpi</code> kernel driver and/or the device tree properties have to be modified for including this functionality.
=== Pins connection ===
