Changes

By default, this signal is connected to on-board ETH PHY reset input. This allows complete software control of PHY reset sequence, even if FPGA is not programmed. In case this signals must  U-Boot <code>board_init</code> software routine generates an hardware reset pulse. This initializes the component to its default register values and then it wil be used to implement different functions on carrier board, alternative routing schemes are available correctly configured for properly working on request in order to free this signalBORA SOM. For more details please refer to department salesLinux kernel will reset the ethernet PHY issuing a software reset via BCMR register.

By default, this signal is connected to on-board USB PHY reset input. This allows complete software control of PHY reset sequence, even if FPGA is not programmed. In case this signals must  U-Boot <code>board_init</code> software routine generates an hardware reset pulse. This initializes the component to its default register values and then it wil be used to implement different functions correctly configured for properly working on carrier board, alternative routing schemes are available on request in order to free this signal. For more details please refer to department salesBORA SOM.