Processor and memory subsystem (Bora)

Info Box Applies to Bora

Processor and memory subsystem

The heart of Bora module is composed of the following components:

• Xilinx Zynq Z-7010 (XC7Z010) / Z-7020 (XC7Z020) SoC
• Power supply unit
• DDR memory banks
• NOR and NAND flash banks
• 3x 140 pin connectors with interfaces signals

This chapter shortly describes the main Bora components.

Processor Info

The Zynq™-7000 family is based on the Xilinx Extensible Processing Platform (EPP) architecture. These products integrate a feature-rich dual-core ARM® Cortex™-A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a single device. The ARM Cortex-A9 CPUs are the heart of the PS and also include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces. The Zynq-7000 family offers the flexibility and scalability of an FPGA, while providing performance, power, and ease of use typically associated with ASIC and ASSPs. The range of devices in the Zynq-7000 AP SoC family enables designers to target cost-sensitive as well as high-performance applications from a single platform using industry-standard tools. While each device in the Zynq-7000 family contains the same PS, the PL and I/O resources vary between the devices. As a result, the Zynq-7000 AP SoC devices are able to serve a wide range of applications including:

• Automotive driver assistance, driver information, and infotainment
• Broadcast camera
• Industrial motor control, industrial networking, and machine vision
• IP and Smart camera
• LTE radio and baseband
• Medical diagnostics and imaging
• Multifunction printers
• Video and night vision equipment

The processors in the PS always boot first, allowing a software centric approach for PL system boot and PL configuration. The PL can be configured as part of the boot process or configured at some point in the future. Additionally, the PL can be completely reconfigured or used with partial, dynamic reconfiguration (PR). PR allows configuration of a portion of the PL. This enables optional design changes such as updating coefficients or time-multiplexing of the PL resources by swapping in new algorithms as needed.

Bora can mount two versions of the Zynq processor. The following table shows a comparison between the processor models, highlighting the differences:

Table: XC7-Z0x0 comparison

Processor	Programmable logic cells	LUTs	Flip flops	Extensible block RAM	DSP slices	Peak DSP performance
XC7Z010	28K Logic Cells	17600	35200	240 KB	80	58 GMACs
XC7Z020	85K Logic Cells	53200	106400	560 KB	220	158 GMACs

On PS side, the following peripherals and devices are connected to MIO signals:

• Serial NOR fl ash (MIO [6:1])
• NAND fl ash (MIO [0], [14:2])
• UART1 (MIO [49:48])
• I2C temperature sensor (MIO [47:46])
• I2C MEMS RTC (MIO [47:46])
• Gigabit Ethernet PHY (MIO [27:16])
• USBOTG PHY (MIO [39:28])
• SD/MMC (MIO [45:40])

Since these devices are considered essential, they have been connected to MIO signals in order to make them always functional, even if PL is not programmed. These peripherals represent the default configuration for the BORA SOM, but other configurations can be implemented changing the pin multiplexing

RAM memory bank

DDR3 SDRAM memory bank is composed by 2x 16-bit width chips resulting in a 32-bit combined width bank. The following table reports the SDRAM specifications:

CPU connection	SDRAM bus
Size min	512 MB
Size max	1 GB
Width	32 bit
Speed	533 MHz

NOR flash bank

NOR flash is a Serial Peripheral Interface (SPI) device. By default this device is connected to SPI channel 0 and acts as boot memory. The following table reports the NOR flash specifications:

CPU connection	SPI Channel 0
Size min	8 MB
Size max	16 MB - This limitation is due to this Errata from Xilinx. The proposed solution by Xilinx has not been approved by DAVE Embedded Systems
Chip select	SPI_CS0n
Bootable	Yes

NAND flash bank

On board main storage memory is a 8-bit wide NAND flash. By default it is connected to chip select. The following table reports the NAND flash specifications:

CPU connection	Static memory controller
Page size	512 byte, 2 kbyte or 4 kbyte
Size min	128 MB
Size max	1 GB
Width	8 bit
Chip select	NAND_CS0
Bootable	Yes

Integrated FPGA

The PL is derived from Xilinx’s 7 Series FPGA technology (Artix™-7 for the 7z010/7z020). The PL is used to extend the functionality to meet specific application requirements. The PL provides many different types of resources including configurable logic blocks (CLBs), port and width configurable block RAM (BRAM), DSP slices with 25 x 18 multiplier, 48-bit accumulator and pre-adder (DSP48E1), a user configurable analog to digital converter (XADC), clock management tiles (CMT), a configuration block with 256b AES for decryption and SHA for authentication, configurable I/Os (with differential signaling capabilities). BORA customers are able to differentiate their product in hardware by customizing their applications using PL.

PL subsystem provides a lot of configurable I/Os, grouped in banks denoted as Bank x (eg Bank 9, Bank 13 etc.). Two types of such banks exist: HR 1 and HP 2. Some of the MIO signals can be routed outside the component via PL subsystem. This technique is called EMIO routing.

Power supply unit

Bora, as the other Ultra Line CPU modules, embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters. For detailed information, please refer to Power Supply Unit page.

CPU module connectors

All interface signals Bora provides are routed through three 140 pin 0.6mm pitch stacking connectors (named J1, J2 and J3). The dedicated carrier board must mount the mating connectors and connect the desired peripheral interfaces according to Bora pinout specifications.