ORCA SOM/ORCA Hardware/Peripherals/MIPI

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Issue Date Notes
2021/02/03 First release

Peripheral MIPI[edit | edit source]

The MIPI interfaces available on iMX8MPlus SoC are following described:

  • The Camera Serial Interface (CSI) is a specification of the Mobile Industry Processor Interface (MIPI) Alliance. It defines an interface between a camera and a host processor.
  • The Display Serial Interface (DSI) is a specification by the Mobile Industry Processor Interface (MIPI) Alliance aimed at reducing the cost of display controllers in a mobile device. It is commonly targeted at LCD and similar display technologies.

The two CSI and the DSI interfaces on ORCA SOM are available on SODIMM connector.

Description[edit | edit source]

The MIPI CSI ports support the following standards and features:

  • MIPI D-PHY specification V1.2
  • Compliant to MIPI CSI2 Specification V1.3 except for C-PHY feature
  • Support primary and secondary Image format
    • YUV420, YUV420 (Legacy), YUV420 (CSPS), YUV422 of 8-bits and 10-bits
    • RGB565, RGB666, RGB888
    • RAW6, RAW7, RAW8, RAW10, RAW12, RAW14
    • All of User defined Byte-based Data packet
  • Support up to 4 lanes of D-PHY
  • Interfaces:
    • Compatible to PPI(Protocol-to-PHY Interface) in MIPI D-PHY Specification
    • AMBA3.0 APB Slave for Register configuration.
    • Image output data buswidth : 32 bits
  • Image memory:
    • Size of SRAM is 4KB
  • Pixel clock can be gated when no ppi data is coming.

The MIPI DSI port supports the following standards and features:

  • Complies to MIPI DSI Standard Specification V1.01r11
    • Maximum resolution ranges up to WQHD (1920x1080p60, 24bpp)
      • It should be decided on bandwidth between input clock (video clock) and output clock (D-PHY HS clock).
    • Supports 1, 2, 3, or 4 data lanes
    • Supports pixel format: 16bpp, 18bpp packed, 18bpp loosely packed (3 byte format), and 24bpp
  • Interfaces:
    • Complies with Protocol-to-PHY Interface (PPI) in 1.0Gbps / 1.5Gbps MIPI D-PHY
    • Supports RGB Interface for Video Image Input from general display controller
  • Supports S-i80(Synchronous i80) Interface for Command Mode Image input from display controller
  • Supports PMS control interface for PLL to configure byte clock frequency
  • Supports Prescaler to generate escape clock from byte clock

Pin mapping[edit | edit source]

The Pin mapping is described in the Pinout table section