ORCA SBC/Interfaces and Connectors/CAN

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Issue Date Notes
2021/12/10 First release

CAN interface[edit | edit source]

Description[edit | edit source]

The CAN interfaces are available on the Evaluation Kit at the connector J8.

J8 is a 20x2x2.54mm pin header expansion connector that delivers many interfaces unused on board and can provide up to two CAN ports.

The CAN bus ports are compatible with the Flexible Data rate (CAN FD) and CAN 2.0B protocols specification.

CAN connector (on J8)

Signals[edit | edit source]

The following table describes the interface signals:

Pin# SOM Pin# Pin name Pin function Pin Notes
10 J15.140 SAI2_RXC CAN1_TX
12 J15.146 SAI2_TXC CAN1_RX
16 J15.148 SAI2_TXD0 CAN2_TX
18 J15.138 SAI2_MCLK CAN2_RX
22 J15.166 SAI5_MCLK CAN2_RX
35 J15.176 SAI5_RXD3 CAN2_TX
36 J15.174 SAI5_RXD2 CAN1_RX
37 J15.172 SAI5_RXD1 CAN1_TX
2, 4 - 5V_VIN Power output for transceiver supply Always ON rail
1, 17 - 3V3_CB Power output for transceiver supply BOARD_PGOOD driven rail
6, 9, 14, 20, 25, 30, 34, 39 - DGND Ground

Please note that all the CAN signals are 0-3.3V level. If a 5V powered transceiver is used, a level shifting is needed to interface to the Evaluation Kit connector.

Device mapping[edit | edit source]

CAN devices are mapped to /dev/can<X> device in Linux. The device mapping depends on the device tree configuration.

Device usage[edit | edit source]

The Evaluation Kit doesn't implement any CAN transceiver, these are needed to mediate between the CAN bus and the CPU module.

The peripheral can be configured using ifconfig and ip link utilities and can be tested with the can-utils utilities.