ONDA SOM/ONDA Hardware/Peripherals/PL

History
Issue Date	Notes
2026/03/25	First documentation release

Programmable logic

The following paragraphs describe in detail the available PL I/O signals and how they are routed to the ONDA connectors. The Zynq Ultrascale+ AP SoC is split into I/O banks to allow for flexibility in the choice of I/O standards, thus each table reports one bank configuration.

Moreover, ONDA design allows carrier board to power all three PL banks in order to achieve complete flexibility in terms of I/O voltage levels too.

For more details about PCB design considerations, please refer to the Advanced routing and carrier board design guidelines article.

The following table reports the I/O banks characteristics:

ONDA bank			FPGA Bank				Bank power supply pins	I/O				Differentials Pairs
Name	Type	External power rail	XCZU4 / XCZU5	XCZU3T	XCZU2	XCZU1		XCZU4 / XCZU5	XCZU3T	XCZU2	XCZU1	XCZU4 / XCZU5	XCZU3T	XCZU2	XCZU1
Bank 43	HD	VDDIO_BANK43-44	Bank 43	-	Bank 44	Bank 44	J3.95 J3.96 J3.97 J3.98 J3.99	24	-	24	24	12	-	12	12
Bank 44			Bank 44	Bank 44	Bank 24	-		24	24	24	-	12	12	12	-
Not connected		-	Bank 45	Bank 45	Bank 25	-	-	-	-	-	-	-	-	-	-
Not connected		-	Bank 46	Bank 46	Bank 26	-	-	-	-	-	-	-	-	-	-
Not connected	HP	-	Bank 64	-	Bank 64	Bank 64	-	-	-	-	-	-	-	-	-
Bank 65		VDDIO_BANK65	Bank 65	-	Bank 65	Bank 65	J1.2 J1.66 J1.67 J1.68	48	-	48	48	24	-	24	24
Bank 66		VDDIO_BANK66	Bank 66	Bank 66	Bank 66	Bank 66		48	48	48	48	24	24	24	24

FPGA I/O Bank definitions:

• HD = High-density I/O with support for I/O voltage from 1.2V to 3.3V
• HP = High-performance I/O with support for I/O voltage from 1.0V to 1.8V

Max I/O

• Max HD I/O available on ONDA SOM is 48 (Bank 43 and Bank 44)
• Max HP I/O available on ONDA SOM is 96 (Bank 65 and Bank 66)

I/O naming

Each user I/O is labeled IO_Lxxy_Tmp_Nb_[opt]_##, where:

• IO indicates a user I/O pin.
• L indicates a differential pair, with xx a unique pair in the bank and y = [P|N] for the positive/negative sides of the differential pair
• T indicates the memory, with m the byte group [0-3] and p = [U|L] Upper/Low portion
• N the number within its b byte group [0 to 12]
• ## indicates the bank number
• [opt] field can be:
  • ADnny indicates a with nn a unique pair in the bank and y = [P|N] for the positive/negative sides of the differential pair
  • GC / HDGC indicates a Global Clock (GC) having access to global clock buffers adjacent to the same I/O bank, and HDGC pins have direct access to the global clock buffers
  • DBC / QBC indicates byte lane clock (DBC and QBC) input pin pairs (clock inputs directly driving source synchronous clocks)
  • VRP indicates a DCI voltage reference resistor of P transistor

GT transceiver

The following table reports the GT transceiver characteristics:

FPGA Bank	Domain	Type	Differentials Pairs				Clock pairs
			XCZU4 / XCZU5	XCZU3T	XCZU2	XCZU1
Bank 505	PS	GTR	4	4	4	4	1
Bank 224	PL	GTH	8	8	-	-	2

• GTR = PS-GTR receivers and transmitters supports up to 6.0Gb/s data rates (supports SGMII tri-speed Ethernet, PCI Express® Gen2, Serial-ATA (SATA), USB3.0, and DisplayPort™)
• GTH = PL-GTH transceiver, on ONDA the maximum data rates is up to 6.0Gb/s