BORA Xpress SOM/BORA Xpress Evaluation Kit/Interfaces and Connectors/Pin strip
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| History | |||
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| Issue Date | Notes | ||
| 2021/11/22 | New documentation layout | ||
Contents
Pin strip[edit | edit source]
Pin strip connectors[edit | edit source]
SPI,NAND - JP13[edit | edit source]
JP13 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
| Pin# | Pin name | Function | Notes |
|---|---|---|---|
| 1, 4, 9, 12 | DGND | Ground | - |
| 2 | SPI0_CS0n | - | - |
| 3 | ZYNQ_SPI0_SCLK/NAND_IO1 | - | - |
| 5 | ZYNQ_SPI0_DQ0/NAND_ALE | - | - |
| 6 | NAND_CS0/SPI0_CS1 | - | - |
| 7 | ZYNQ_SPI0_DQ2/NAND_IO2 | - | - |
| 8 | ZYNQ_SPI0_DQ1/NAND_WE | - | - |
| 10 | ZYNQ_SPI0_DQ3/NAND_IO0 | - | - |
| 11 | ZYNQ_NAND_RD_B | - | - |
Voltage Monitor - JP15[edit | edit source]
JP15 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
| Pin# | Pin name | Function | Notes |
|---|---|---|---|
| 1 | MON_VCCPLL | - | - |
| 2 | MON_3.3V | - | - |
| 3 | MON_XADC_VCC | - | - |
| 4 | MON_1V2_ETH | - | - |
| 5 | MON_FPGA_VDDIO_BANK35 | - | - |
| 6 | MON_VDDQ_1V5 | - | - |
| 7 | MON_FPGA_VDDIO_BANK34 | - | - |
| 8 | MON_1.8V | - | - |
| 9 | MON_FPGA_VDDIO_BANK13 | - | - |
| 10 | MON_1.0V | - | - |
| 11 | MON_1.8V_IO | - | - |
| 12 | MON_MGTAVCC | - | - |
| 13 | MON_MGTAVTT | - | - |
| 14 | MON_MGTAVCCAUX | - | - |
| 15, 16 | DGND | Ground | - |
Ethernet GPIO - JP18[edit | edit source]
JP18 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
| Pin# | Pin name | Function | Notes |
|---|---|---|---|
| 1, 2, 5, 6, 16 |
DGND | Ground | - |
| 3 | CLK125_NDO | - | - |
| 4 | ETH1_CLK125_NDO | - | - |
| 7 | ETH_MDC | - | - |
| 8 | ETH1_MDC | - | - |
| 9 | ETH_MDIO | - | - |
| 10 | ETH1_MDIO | - | - |
| 11 | ETH_INTn | - | - |
| 12 | ETH1_INTn | - | - |
| 13 | PS_MIO51_501 | - | - |
| 14 | ETH1_RESETn | - | - |
| 15 | PS_MIO50_501 | - | - |
SPI,NAND - JP19[edit | edit source]
JP19 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
| Pin# | Pin name | Function | Notes |
|---|---|---|---|
| 1, 11, 12 | DGND | Ground | - |
| 2 | NAND_BUSY | - | - |
| 3 | ZYNQ_NAND_CLE | - | - |
| 4 | NAND_IO3 | - | - |
| 5 | NAND_IO4 | - | - |
| 6 | NAND_IO5 | - | - |
| 7 | NAND_IO6 | - | - |
| 8 | NAND_IO7 | - | - |
| 9 | CONN_SPI_RSTn | - | - |
| 10 | MEM_WPn | - | - |
