BORA SOM/BORA Evaluation Kit/Interfaces and Connectors/Pin strip
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Contents
Pin strip[edit | edit source]
Pin strip connectors[edit | edit source]
ADC - JP10[edit | edit source]
JP10 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
| Pin# | Pin name | Function | Notes |
|---|---|---|---|
| 1 | IO_0_35 | - | - |
| 2, 4 | VDDIO_BANK35 | - | - |
| 3, 6, 9, 12, 15 | XADC_GND | - | - |
| 5 | ZYNQ_AD14P_35 | - | Mount option |
| 7 | ZYNQ_AD14N_35 | - | Mount option |
| 8 | ZYNQ_T0_VREF_35 | - | Mount option |
| 10 | ZYNQ_T3_VREF_35 | - | Mount option |
| 11 | ZYNQ_AD1P_35 | - | Mount option |
| 13 | ZYNQ_AD1N_35 | - | Mount option |
| 14 | ZYNQ_AD3P_35 | - | Mount option |
| 16 | ZYNQ_AD3N_35 | - | Mount option |
SPI,NAND - JP13[edit | edit source]
JP13 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
| Pin# | Pin name | Function | Notes |
|---|---|---|---|
| 1, 4, 9, 12 | DGND | Ground | - |
| 2 | SPI0_CS0n | - | - |
| 3 | ZYNQ_SPI0_SCLK/NAND_IO1 | - | - |
| 5 | ZYNQ_SPI0_DQ0/NAND_ALE | - | - |
| 6 | NAND_CS0/SPI0_CS1 | - | - |
| 7 | ZYNQ_SPI0_DQ2/NAND_IO2 | - | - |
| 8 | ZYNQ_SPI0_DQ1/NAND_WE | - | - |
| 10 | ZYNQ_SPI0_DQ3/NAND_IO0 | - | - |
| 11 | ZYNQ_NAND_RD_B | - | - |
Voltage Monitor - JP15[edit | edit source]
JP15 is a 12-pin 6x2x2.00 pitch vertical header. The following table reports the pinout of the connector:
| Pin# | Pin name | Function | Notes |
|---|---|---|---|
| 1 | MON_VCCPLL | - | - |
| 2 | MON_3.3V | - | - |
| 3 | MON_XADC_VCC | - | - |
| 4 | MON_1V2_ETH | - | - |
| 5 | MON_FPGA_VDDIO_BANK35 | - | - |
| 6 | MON_VDDQ_1V5 | - | - |
| 7 | MON_FPGA_VDDIO_BANK34 | - | - |
| 8 | MON_1.8V | - | - |
| 9 | MON_FPGA_VDDIO_BANK13 | - | - |
| 10 | MON_1.0V | - | - |
| 11 | MON_1.8V_IO | - | - |
| 12 | DGND | Ground | - |
Ethernet GPIO - JP18[edit | edit source]
JP18 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
| Pin# | Pin name | Function | Notes |
|---|---|---|---|
| 1, 2, 5, 6, 16 |
DGND | Ground | - |
| 3 | CLK125_NDO | - | - |
| 4 | ETH1_CLK125_NDO | - | - |
| 7 | ETH_MDC | - | - |
| 8 | ETH1_MDC | - | - |
| 9 | ETH_MDIO | - | - |
| 10 | ETH1_MDIO | - | - |
| 11 | ETH_INTn | - | - |
| 12 | ETH1_INTn | - | - |
| 13 | PS_MIO51_501 | - | - |
| 14 | ETH1_RESETn | - | - |
| 15 | PS_MIO50_501 | - | - |
SPI,NAND - JP19[edit | edit source]
JP19 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
| Pin# | Pin name | Function | Notes |
|---|---|---|---|
| 1, 11, 12 | DGND | Ground | - |
| 2 | NAND_BUSY | - | - |
| 3 | ZYNQ_NAND_CLE | - | - |
| 4 | NAND_IO3 | - | - |
| 5 | NAND_IO4 | - | - |
| 6 | NAND_IO5 | - | - |
| 7 | NAND_IO6 | - | - |
| 8 | NAND_IO7 | - | - |
| 9 | CONN_SPI_RSTn | - | - |
| 10 | MEM_WPn | - | - |
ADC - JP20[edit | edit source]
JP20 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
| Pin# | Pin name | Function | Notes |
|---|---|---|---|
| 1 | VDDIO_BANK35 | - | - |
| 2, 6, 11, 12 |
XADC_AGND | - | - |
| 3 | ZYNQ_AD0P_35 | - | - |
| 4 | MON_XADC_VCC | - | - |
| 5 | ZYNQ_AD15P_35 | - | - |
| 7 | ZYNQ_AD15N_35 | - | - |
| 8 | XADC_VN_R | - | - |
| 9 | ZYNQ_AD2P_35 | - | - |
| 10 | XADC_VP_R | - | - |
I2C, BANK34 - JP21[edit | edit source]
JP21 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
| Pin# | Pin name | Function | Notes |
|---|---|---|---|
| 1 | EVB_1.8V | - | - |
| 2 | 3.3V | - | - |
| 3 | PS_I2C0_DAT | - | - |
| 4 | I2C0_SDA | - | - |
| 5 | PS_I2C0_CK | - | - |
| 6 | I2C0_SCL | - | - |
| 7, 8, 12, 13 |
DGND | Ground | - |
| 9 | IO_L6P_T0_34 | CAN Transmitter | - |
| 10 | INA_ALERT | - | - |
| 11 | IO_L19P_T3_34 | CAN Receiver | - |
| 14 | IO_L3P_T0_DQS_PUDC_B_34 | - | - |
| 15 | IO_25_34 | - | - |
| 16 | IO_0_34 | - | - |
Please note that:
- Three devices are connected to I2C0 bus (this is level shifted from 1.8V to 3.3V):
- Silicon Labs Si571 programmable clock generator: this clock si connected to PL to allow the user to easily experiment his/her own peripherals and IPs on FPGA
- resistive touch screen controller for LCD screen
- consumption monitor: this is connected to shunt resistor put in series on Bora power rail, allowing to measure SoM consumption
FPGA, WatchDog, RTC, RST - JP22[edit | edit source]
JP22 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
| Pin# | Pin name | Function | Notes |
|---|---|---|---|
| 1 | FPGA_INIT_B | - | - |
| 2 | RTC_32KHZ | - | - |
| 3 | FPGA_PROGRAM_B | - | - |
| 4 | RTC_RST | - | - |
| 5 | FPGA_DONE | - | - |
| 6 | RTC_INT/SQW | - | - |
| 7, 8 | DGND | Ground | - |
| 9 | WD_SET0 | - | - |
| 10 | SYS_RSTn | - | - |
| 11 | WD_SET1 | - | - |
| 12 | PORSTn | - | - |
| 13 | WD_SET2 | - | - |
| 14 | MRSTn | - | - |
| 15 | PS_MIO15_500 | - | - |
| 16 | CB_PWR_GOOD | - | - |
