BORA SOM/BORA Evaluation Kit/Interfaces and Connectors/LVDS

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Issue Date Notes
2021/10/28 New documentation layout


LVDS[edit | edit source]

LVDS - J26[edit | edit source]

J26 is a vertical double row straight 20-pin 1.25mm pitch header. This interface shows how to implement a differential connection to an LCD screen. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki.analog.com/resources/tools-software/linux-drivers/platforms/zynq. The following table reports the pinout of the connector:

Pin# Pin name Function Notes
1, 2 3.3V_LCD - -
3, 4, 7, 10,
13, 16, 19
DGND Ground -
5 LCD_LVDS_D0- - -
6 LCD_LVDS_D0+ - -
8 LCD_LVDS_D1- - -
9 LCD_LVDS_D1+ - -
11 LCD_LVDS_D2- - -
12 LCD_LVDS_D2+ - -
15 LCD_LVDS_CLK+ - -
17 LCD_P17 - -
18 LCD_P18 - -
20 LCD_P20 - -
21,22 DGND Ground Shield