AXEL ULite SOM/AXEL ULite Evaluation Kit/Interfaces and Connectors/LVDS
History | |||
---|---|---|---|
Version | Issue Date | Notes | |
1.0.0 | Jul 2021 | First DESK release |
LVDS interface[edit | edit source]
Description[edit | edit source]
The LVDS interface available on the Evaluation Kit at the connector J20. J20 is a Hirose (cod. DF13A-20DP-1.25V) double row 1.25mm pitch miniature crimping connector
The AXEL ULite Evaluation Kit provides a 18-bit LVDS interface.
Signals[edit | edit source]
The LVDS is generated, starting from the RGB i.MX6UL SOC, with a RGB-to-LVDS DS90C385A LVDS transmitter. For the RGB pin mapping, please refer to the AXEL_ULite RGB interface description.
The following tables describes the interface signals:
Pin# | Pin name | Pin function |
---|---|---|
1, 2 | 3.3V_LCD | 3.3 V LCD PSU |
3, 4, 7, 10,
13, 16, 19 |
- | Ground |
5 | LVDS_TX0_N | LVDS Data 0 - |
6 | LVDS_TX0_P | LVDS Data 0 + |
8 | LVDS_TX1_N | LVDS Data 1 - |
9 | LVDS_TX1_P | LVDS Data 1 + |
11 | LVDS_TX2_N | LVDS Data 2 - |
12 | LVDS_TX2_P | LVDS Data 2 + |
14 | LVDS_CLK_N | LVDS Clock - |
15 | LVDS_CLK_P | LVDS Clock + |
17 | PWM | backlight PWM control |
18 | 5V | backlight 5V PSU |
19 | GPIO | 3V3 or GND (mount option, default = GND) |
20 | BL_EN | backlight enable |
Device mapping[edit | edit source]
- LVDS is mapped to
/dev/fb0
device in Linux