AURA SOM/AURA Hardware/Peripherals/UART

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History
Issue Date Notes
2023/09/13 First release



Peripheral UART[edit | edit source]

LPUART provides asynchronous, serial communication capabilities with external devices. LPUART can continue operating when the processor is in Low-Power mode, if an appropriate peripheral clock is available.

The UART interface available on AURA is based on i.MX93 SoC. The chip includes eight instances of UART Modules:

  • LPUART1 and LPUART2 are in Low Power Real Time Domain
  • LPUART[3..8] are in Application Flex Domain

Description[edit | edit source]

The UART port supports the following standards and features:

  • Full-duplex, standard NRZ format
  • Programmable baud rates (13-bit modulo divider) with a configurable oversampling ratio
  • Asynchronous operations of transmit and receive baud rates with respect to the bus clock
  • Interrupt, DMA, or polled operations
  • Hardware parity generation and checking
  • Programmable 7-bit, 8-bit, 9-bit, or 10-bit character length
  • Programmable 1-bit or 2-bit stop bits
  • Hardware flow control support for request to send (RTS) and clear to send (CTS) signals
  • Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with a programmable pulse width

Pin mapping[edit | edit source]

The Pin mapping is described in the Pinout table section