AURA SOM/AURA Hardware/Peripherals/I3C
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Peripheral I3C[edit | edit source]
The MIPI Alliance Improved Inter-Integrated Circuit (MIPI I3C) improves upon the use and power of I2C, and provides an alternative to SPI for mid-speed applications.
The I3C interface available on AURA is based on i.MX93 SoC. The chip includes two instances of I3C Modules:
- I3C1 is in Low Power Real Time Domain
- I3C2 is in Application Flex Domain
Description[edit | edit source]
The I3C bus protocol supports:
- all required and most optional features of the MIPI Alliance Specification for I3C, v1.0 and v1.1, except for ternary data rates (HDR-TSP and HDR-TSL)
- In-band interrupts (IBI)
- Common Command Codes (CCC)
- Dynamic addressing
- Multi-controller/multi-drop
- Hot-Join (HJ)
- I2C compatibility
Pin mapping[edit | edit source]
The Pin mapping is described in the Pinout table section
