AURA SOM/AURA Hardware/Peripherals/I2C

History
Issue Date	Notes
2023/09/13	First release

Peripheral I2C

LPI2C is a low-power Inter-Integrated Circuit (I2C) module that supports an efficient interface to an I2C bus as a controller and/or as a target.

The I2C interface available on AURA is based on i.MX93 SoC. The chip includes eight instances of LPI2C Modules:

• LPI2C1 and LPI2C2 are in Low Power Real Time Domain
• LPI2C[3..8] are in Application Flex Domain

Description

The LPI2C port supports the following standards and features:

• Compliance with the System Management Bus (SMBus) Specification, version 3
• Standard, Fast, Fast+ and Ultra Fast modes
• High-speed mode (HS) in target mode
• Multi-controller, including synchronization and arbitration
• Clock stretching
• General call, seven-bit addressing, and ten-bit addressing
• Software reset, START byte, and Device ID

The LPI2C controller supports:

• Command/transmit/receive FIFO of 8 words (8-bit transmit data + 3-bit command or 8-bit receive data)
  • Command FIFO waits for idle I2C bus before initiating transfer.
• Flags and optional interrupt signals at repeated START condition, STOP condition, loss of arbitration, unexpected NACK, and command word errors
• Configurable bus idle timeout and pin-stuck-low timeout.

The LPI2C target supports:

• Separate I2C target registers
• 7-bit or 10-bit addressing, address range, SMBus alert, and general call address
• Transmit/Receive data register that supports interrupt or DMA requests
• Software-controllable ACK or NACK, with optional clock stretching on ACK/NACK bit
• Configurable clock stretching
• Flags and optional interrupt at end of packet, STOP condition, or bit error detection

Pin mapping

The Pin mapping is described in the Pinout table section

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