AURA SOM/AURA Hardware/Peripherals/CAN

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Issue Date Notes
2023/09/12 First release

Peripheral CAN[edit | edit source]

The CAN interface available on AURA is based on i.MX93 SoC. The SOC includes two instances of CAN-FD Controllers (CAN-FD1 is in AONMIX and CAN-FD2 is in WAKEUPMIX).

The FlexCAN module is a full implementation of the CAN with Flexible Data Rate (CAN FD) protocol specification and CAN protocol specification, Version 2.0 B compliant with the ISO 11898-1:2015 standard

Description[edit | edit source]

The FlexCAN module includes these distinctive features:

  • Flexible mailboxes configurable to store 0 to 8, 16, 32, or 64 bytes data length
    • Each mailbox configurable as receive or transmit, all supporting standard and extended messages
  • Individual Rx Mask registers per mailbox
  • Full-featured
    • legacy Rx FIFO with storage capacity for up to six frames and automatic internal pointer handling with DMA support
    • enhanced Rx FIFO with storage capacity for up to 20 CAN FD frames
  • Transmission abort capability
  • Flexible message buffers (MBs), totaling 96 message buffers of 8 bytes data length each, configurable as Rx or Tx
  • Programmable
    • Loop-Back mode supporting self-test operation
    • Programmable transmission priority scheme: lowest ID, lowest buffer number, or highest priority
  • Time stamp based on 32-bit free running timer, with an optional external time tick
  • Short latency time due to an arbitration scheme for high-priority messages
  • Low power modes, with programmable wakeup on bus activity
  • Powerful
    • legacy Rx FIFO ID filtering, capable of matching incoming IDs against either 128 extended, 256 standard, or 512 partial (8 bit) IDs, with up to 32 individual masking capability
    • Enhanced Rx FIFO ID filtering, capable of matching incoming IDs against either 64 extended or 128 standard ID filter elements with three filtering schemes: mask + filter, range, and two filters without mask

Pin mapping[edit | edit source]

The Pin mapping is described in the Pinout table section