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== Introduction ==
The following paragraphs describe in detail the available PL I/O pins signals and how they are routed to the BORA Xpress connectors. The Zynq-7000 AP SoC is split into I/O banks to allow for flexibility in the choice of I/O standards, thus each table reports one bank configuration. Moreover, BORA Xpress design allows carrier board to power two all three PL banks in order to achieve complete flexibility in terms of I/O voltage levels too.
For more details about PCB design considerations, please refer to the [[Integration_guide_(BORAXpress)#Advanced_routing_and_carrier_board_design_guidelines | Advanced routing and carrier board design guidelines]] article.
|-
!FPGA Bank
!I/O VoltageXC7Z015!XC7Z030
!Voltage Pins
!NotesI/O!Differentials Pairs|-|Bank 13|HR|HR|J3.95<br>J3.96<br>J3.97<br>J3.98<br>J3.99|50|24|-|Bank 34|HR|HP|J2.66<br>J2.68<br>J2.70<br>J2.72|50|24|-|Bank 35|HR|HP|J1.2<br>J1.66<br>J1.67<br>J1.68|50|24
|-
|}
FPGA I/O Bank definitions:
* '''HR''' = High Range I/O with support for I/O voltage from 1.2V to 3.3V
* '''HP''' = High Performance I/O with support for I/O voltage from 1.2V to 1.8V
Each user I/O is labeled IO_LXXY_Tn_ZZZ_ADi_#, where:
* # indicates the bank number.