devwiki_user
145
edits
Changes
Created page with "{{InfoBoxTop}} {{Applies To BoraX}} {{InfoBoxBottom}} == Introduction == The following paragraphs describe in detail the available PL I/O pins and how they are routed to the..."
{{InfoBoxTop}}
{{Applies To BoraX}}
{{InfoBoxBottom}}
== Introduction ==
The following paragraphs describe in detail the available PL I/O pins and how they are routed to the BORA Xpress connectors. The Zynq-7000 AP SoC is split into I/O banks to allow for flexibility in the choice of I/O standards, thus each table reports one bank configuration. Moreover, BORA Xpress design allows carrier board to power two PL banks in order to achieve complete flexibility in terms of I/O voltage levels too.
For more details about PCB design considerations, please refer to the [[Integration_guide_(BORAXpress)#Advanced_routing_and_carrier_board_design_guidelines | Advanced routing and carrier board design guidelines]] article.
The following table reports the I/O banks characteristics:
{| class="wikitable"
|-
!FPGA Bank
!I/O Voltage
!Voltage Pins
!Notes
|-
|}
Each user I/O is labeled IO_LXXY_Tn_ZZZ_ADi_#, where:
* IO indicates a user I/O pin.
* L indicates a differential pair, with XX a unique pair in the bank and Y = [P|N] for the positive/negative sides of the differential pair.
* Tn indicates the memory byte group [0-3]
* ZZZ indicates a MRCC, SRCC or DQS pin
* ADi indicates a XADC (analog-to-digital converter) differential auxiliary analog input [0–15].
* # indicates the bank number.
Highlighted rows are related to signals that are used for particular functions into the SOM.
== FPGA Bank x ==
The following table reports the available pins connected to bank x:
{| class="wikitable" border="1"
| align="left" style="background:#f0f0f0;"|'''Pin Name'''
| align="left" style="background:#f0f0f0;"|'''Conn. Pin'''
| align="left" style="background:#f0f0f0;"|'''Notes'''
|-
|}
== FPGA Bank y ==
The following table reports the available pins connected to bank y:
{| class="wikitable" border="1"
| align="left" style="background:#f0f0f0;"|'''Pin Name'''
| align="left" style="background:#f0f0f0;"|'''Conn. Pin'''
| align="left" style="background:#f0f0f0;"|'''Notes'''
|-
|}
== FPGA Bank z ==
The following table reports the available pins connected to bank z:
{| class="wikitable" border="1"
| align="left" style="background:#f0f0f0;"|'''Pin Name'''
| align="left" style="background:#f0f0f0;"|'''Conn. Pin'''
| align="left" style="background:#f0f0f0;"|'''Notes'''
|-
|}
{{Applies To BoraX}}
{{InfoBoxBottom}}
== Introduction ==
The following paragraphs describe in detail the available PL I/O pins and how they are routed to the BORA Xpress connectors. The Zynq-7000 AP SoC is split into I/O banks to allow for flexibility in the choice of I/O standards, thus each table reports one bank configuration. Moreover, BORA Xpress design allows carrier board to power two PL banks in order to achieve complete flexibility in terms of I/O voltage levels too.
For more details about PCB design considerations, please refer to the [[Integration_guide_(BORAXpress)#Advanced_routing_and_carrier_board_design_guidelines | Advanced routing and carrier board design guidelines]] article.
The following table reports the I/O banks characteristics:
{| class="wikitable"
|-
!FPGA Bank
!I/O Voltage
!Voltage Pins
!Notes
|-
|}
Each user I/O is labeled IO_LXXY_Tn_ZZZ_ADi_#, where:
* IO indicates a user I/O pin.
* L indicates a differential pair, with XX a unique pair in the bank and Y = [P|N] for the positive/negative sides of the differential pair.
* Tn indicates the memory byte group [0-3]
* ZZZ indicates a MRCC, SRCC or DQS pin
* ADi indicates a XADC (analog-to-digital converter) differential auxiliary analog input [0–15].
* # indicates the bank number.
Highlighted rows are related to signals that are used for particular functions into the SOM.
== FPGA Bank x ==
The following table reports the available pins connected to bank x:
{| class="wikitable" border="1"
| align="left" style="background:#f0f0f0;"|'''Pin Name'''
| align="left" style="background:#f0f0f0;"|'''Conn. Pin'''
| align="left" style="background:#f0f0f0;"|'''Notes'''
|-
|}
== FPGA Bank y ==
The following table reports the available pins connected to bank y:
{| class="wikitable" border="1"
| align="left" style="background:#f0f0f0;"|'''Pin Name'''
| align="left" style="background:#f0f0f0;"|'''Conn. Pin'''
| align="left" style="background:#f0f0f0;"|'''Notes'''
|-
|}
== FPGA Bank z ==
The following table reports the available pins connected to bank z:
{| class="wikitable" border="1"
| align="left" style="background:#f0f0f0;"|'''Pin Name'''
| align="left" style="background:#f0f0f0;"|'''Conn. Pin'''
| align="left" style="background:#f0f0f0;"|'''Notes'''
|-
|}
