Changes

The following paragraphs describe in detail the available PL I/O pins signals and how they are routed to the BORA Xpress connectors. The Zynq-7000 AP SoC is split into I/O banks to allow for flexibility in the choice of I/O standards, thus each table reports one bank configuration. Moreover, BORA Xpress design allows carrier board to power two all three PL banks in order to achieve complete flexibility in terms of I/O voltage levels too.

!I/O VoltageXC7Z015!XC7Z030

!NotesI/O!Differentials Pairs|-|Bank 13|HR|HR|J3.95<br>J3.96<br>J3.97<br>J3.98<br>J3.99|50|24|-|Bank 34|HR|HP|J2.66<br>J2.68<br>J2.70<br>J2.72|50|24|-|Bank 35|HR|HP|J1.2<br>J1.66<br>J1.67<br>J1.68|50|24

Highlighted rows are related to signals that are Here is a list of FPGA I/O actually used for particular functions into the inside BORA Xpress SOM. == FPGA Bank x == The following table reports the available pins connected to bank x: {| class="wikitable" border="1"| align="left" style="background:#f0f0f0;"|'''Pin Name'''| align="left" style="background:#f0f0f0;"|'''Conn. Pin'''| align="left" style="background* IO_L6P_T0_34 :#f0f0f0;"|'''Notes'''|-|}CAN_RX== FPGA Bank y ==The following table reports the available pins connected to bank y* IO_L19P_T3_34 : {| class="wikitable" border="1"| align="left" style="background:#f0f0f0;"|'''Pin Name'''| align="left" style="background:#f0f0f0;"|'''Conn. Pin'''| align="left" style="background:#f0f0f0;"|'''Notes'''|-|} == FPGA Bank z == The following table reports the available pins connected to bank z: {| class="wikitable" border="1"| align="left" style="background:#f0f0f0;"|'''Pin Name'''| align="left" style="background:#f0f0f0;"|'''Conn. Pin'''| align="left" style="background:#f0f0f0;"|'''Notes'''|-|}CAN_TX