User contributions
16 October 2019
RTC (Bora)
U0007 moved page RTC (Bora) to RTC (Bora/BoraLite)
RTC (Bora/BoraLite)
U0007 moved page RTC (Bora) to RTC (Bora/BoraLite)
mRTC (Bora/BoraLite)
no edit summary
+93
Watchdog (BoraLite)
Created page with "{{InfoBoxTop}} {{Applies To BoraLite}} {{InfoBoxBottom}} ==Description and default configuration== An external watchdog timer (WDT), Maxim MAX6373<ref name="MAX6373">https://..."
System boot and recovery via microSD card (BELK/BXELK)
no edit summary
+24
Standalone boot (BELK/BXELK)
no edit summary
+24
Restoring U-Boot on SPI NOR flash (BELK/BXELK)
no edit summary
+24
Category:BoraLite
Hardware Documentation
+2
Processing system peripherals (BoraLite)
Created page with "{{InfoBoxTop}} {{Applies To BoraLite}} {{InfoBoxBottom}} == Introduction == Bora modules implement a number of peripheral interfaces through the J1 connector. The following..."
Product serial number
no edit summary
+24
Mechanicals (BoraLite)
Created page with "{{InfoBoxTop}} {{Applies To BoraLite}} {{InfoBoxBottom}} = Mechanical specifications = This chapter describes the mechanical characteristics of the BORA Lite module. == Boa..."
Logical structure of Bora and BoraX Embedded Linux Kits (BELK/BXELK)
no edit summary
+24
Introduction to development environment (BELK/BXELK)
no edit summary
+24
Host setup and development flow (BELK/BXELK)
no edit summary
+24
ConfigID management (BELK/BXELK)
no edit summary
+575
Programmable logic (BORAXpress)
Introduction
Programmable logic (BoraLite)
no edit summary
+20,244
Programmable logic (Bora)
FPGA Bank 34
Category:Bora
Hardware Documentation
+6
Pinout (BoraLite)
J1 odd pins (1 to 203)
+4
Programmable logic (BoraLite)
Created page with "{{InfoBoxTop}} {{Applies To BoraLite}} {{InfoBoxBottom}} == Introduction == The following paragraphs describe in detail the available PL I/O pins and how they are routed to..."
15 October 2019
Build system (BELK/BXELK)
no edit summary
+24
ConfigID and UniqueID
DAVE Embedded Systems' hardware implementation
+142
Category:BoraLite
Software Documentation
+2
Category:BoraX
Software Documentation
+2
On board JTAG connector (AxelLite)
Undo revision 9016 by U0007 (talk)
-754
On board JTAG connector (AxelLite)
Undo revision 9018 by U0007 (talk)
+754
On board JTAG connector (AxelLite)
Reverted edits by U0007 (talk) to last revision by DevWikiAdmin
m-754
On board JTAG connector (BoraLite)
Created page with "{{InfoBoxTop}} {{Applies To BoraLite}} {{InfoBoxBottom}} == Introduction == JTAG signals are routed to a dedicated connector (J2) on the BORA Lite PCB. The connector is plac..."
On board JTAG connector (AxelLite)
no edit summary
+754
FAQs (Bora/BoraX)
U0007 moved page FAQs (Bora/BoraX) to FAQs (Bora/BoraX/BoraLite)
FAQs (Bora/BoraX/BoraLite)
U0007 moved page FAQs (Bora/BoraX) to FAQs (Bora/BoraX/BoraLite)
mBoraXEVB
no edit summary
+24
Booting the system via NFS (BELK/BXELK)
no edit summary
+45
Booting Linux Kernel
no edit summary
+45
FAQs (Bora/BoraX/BoraLite)
no edit summary
+24
Development Kits Identification Codes
no edit summary
+24
Creating and building example Vivado project (BELK/BXELK)
no edit summary
+2
Creating and building example Vivado project (BELK/BXELK)
no edit summary
+22
ConfigID and UniqueID
no edit summary
+24
Carrier board design guidelines (SOM)
no edit summary
+24
Building Linux kernel (BELK/BXELK)
no edit summary
+24
Building the Yocto BSP (BELK/BXELK)
no edit summary
+24
Building U-Boot (BELK/BXELK)
no edit summary
+24
Template:Applies To BoraLite
Created page with "<div style="float:left;border:solid #00ffcc 1px;margin:1px"> {| cellspacing="0" style="width:238px;background:#c5fcdc" | style="width:45px;height:45px;background:#6ef7a7;text-..."
Pinout (BoraLite)
Introduction
+9
Pinout (BoraLite)
no edit summary
Pinout (BoraLite)
J1 even pins (2 to 204)
Pinout (BoraLite)
J1 odd pins (1 to 203)
+6
Pinout (BoraLite)
J1 odd pins (1 to 203)
+83