Bureaucrats, dave_user, Administrators
8,157
edits
Changes
→J1 odd pins (1 to 203)
|-
|J1.73||DGND||DGND||n.a.||||||||
|-|J1.75||ETH0_PHY_RST||LAN.RESET_N||41||||||||Internally connected to PS_MIO51_501
|-
|J1.77||VDDIO_BANK34||FPGA.VCCO_BANK34||N19<br>R15<br>T18<br>V14<br>W17<br>Y20||||||||
