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Created page with "{{InfoBoxTop}} {{Applies To BoraLite}} {{InfoBoxBottom}} == Introduction == JTAG signals are routed to a dedicated connector (J2) on the BORA Lite PCB. The connector is plac..."
{{InfoBoxTop}}
{{Applies To BoraLite}}
{{InfoBoxBottom}}
== Introduction ==
JTAG signals are routed to a dedicated connector (J2) on the BORA Lite PCB. The connector is placed on the top side of the PCB, at the upper-right corner (please see the picture below).
[[File:BORAlite-jtag-conn.png|500px|frameless|border]]
== J2 - Connector's pinout ==
J2 footprint mates with Samtec FSI-110-03-G-S connector. The following table reports the connector's pinout:
{| class="wikitable"
|-
!Pin#
!Pin name
!Function
!Notes
|-
|1 || DGND || - || -
|-
|2 || JTAG_TCK || - || -
|-
|3 || JTAG_TMS || - || -
|-
|4 || JTAG_TDO || - || -
|-
|5 || JTAG_TDI || - || -
|-
|6 || FPGA_INIT_B || - || Place external 4.7 kO (or stronger) pull-up resistor to BOARD_PGOOD driven +3.3V supply
For more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]
|-
|7 || FPGA_PROGRAM_B || - || Place external 4.7 kO (or stronger) pull-up resistor to BOARD_PGOOD driven +3.3V supply
For more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]
|-
|8 || FPGA_DONE || - || Place external 300O pull-up resistor to BOARD_PGOOD driven +3.3V supply
For more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]
|-
|9 || N.C. || - || -
|-
|10 || 3V3 || - || 3.3VIN enabled with BOARD_PGOOD
|-
|}
{{Applies To BoraLite}}
{{InfoBoxBottom}}
== Introduction ==
JTAG signals are routed to a dedicated connector (J2) on the BORA Lite PCB. The connector is placed on the top side of the PCB, at the upper-right corner (please see the picture below).
[[File:BORAlite-jtag-conn.png|500px|frameless|border]]
== J2 - Connector's pinout ==
J2 footprint mates with Samtec FSI-110-03-G-S connector. The following table reports the connector's pinout:
{| class="wikitable"
|-
!Pin#
!Pin name
!Function
!Notes
|-
|1 || DGND || - || -
|-
|2 || JTAG_TCK || - || -
|-
|3 || JTAG_TMS || - || -
|-
|4 || JTAG_TDO || - || -
|-
|5 || JTAG_TDI || - || -
|-
|6 || FPGA_INIT_B || - || Place external 4.7 kO (or stronger) pull-up resistor to BOARD_PGOOD driven +3.3V supply
For more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]
|-
|7 || FPGA_PROGRAM_B || - || Place external 4.7 kO (or stronger) pull-up resistor to BOARD_PGOOD driven +3.3V supply
For more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]
|-
|8 || FPGA_DONE || - || Place external 300O pull-up resistor to BOARD_PGOOD driven +3.3V supply
For more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]
|-
|9 || N.C. || - || -
|-
|10 || 3V3 || - || 3.3VIN enabled with BOARD_PGOOD
|-
|}