User contributions
6 November 2015
BELK-TN-001: Real-timeness, system integrity and TrustZone® technology on AMP configuration
L2 cache management
+359
BELK-TN-001: Real-timeness, system integrity and TrustZone® technology on AMP configuration
Limitations of traditional configurations
-130
5 November 2015
BELK-TN-001: Real-timeness, system integrity and TrustZone® technology on AMP configuration
L2 cache management
+1
BELK-TN-001: Real-timeness, system integrity and TrustZone® technology on AMP configuration
Overview
-100
BELK-TN-001: Real-timeness, system integrity and TrustZone® technology on AMP configuration
L2 cache management
+33
BELK-TN-001: Real-timeness, system integrity and TrustZone® technology on AMP configuration
Inter-world communication
BELK-TN-001: Real-timeness, system integrity and TrustZone® technology on AMP configuration
References
BELK-TN-001: Real-timeness, system integrity and TrustZone® technology on AMP configuration
Conclusions and future work
+80
Thermal IC (BORAXpress)
no edit summary
Reset scheme (BORAXpress)
PORSTn (J2.114)
BoraXEVB
Connectors pinout
-186
BoraXEVB
FPGA Mezzanine Card (FMC) Connector - J27
-3
BoraXEVB
Block Diagram
BoraXEVB
Block Diagram
+53
BoraXEVB
no edit summary
-5
BORA Xpress SOM
no edit summary
-94
Creating and building example Vivado project (BELK/BXELK)
GUI based procedure
-2,033
Creating and building example Vivado project (BELK/BXELK)
Command line based procedure
+7
Creating and building example Vivado project (BELK/BXELK)
Command line based procedure
-1,763
Programmable logic (BORAXpress)
Routing Information
+72
Mechanicals (BORAXpress)
CAD drawings
+197
4 November 2015
FAQs (Axel)
Q: How can I change the CPU clock frequency?
+186
Bora Embedded Linux Kit (BELK)
BELK 2.1.0
+33
Advanced use of Yocto build system (BELK/BXELK)
no edit summary
+126
ConfigID management (BELK/BXELK)
no edit summary
-2,192
BoraXEVB
Created page with "{{InfoBoxTop}} {{Applies To BoraX}} {{InfoBoxBottom}}"
Integration guide (Bora)
U0001 moved page Integration guide (Bora) to Integration guide (Bora/BoraX)
Integration guide (Bora/BoraX/BoraLite)
U0001 moved page Integration guide (Bora) to Integration guide (Bora/BoraX)
mIntegration guide (Bora/BoraX/BoraLite)
no edit summary
+21
Integration guide (Bora/BoraX/BoraLite)
Programmable logic (PL)
+77
Programmable logic (BORAXpress)
Introduction
+10
Creating and building example Vivado project (BELK/BXELK)
no edit summary
+2,059
Creating and building example Vivado project (BELK/BXELK)
GUI based procedure
+2,592
Watchdog (BORAXpress)
Description and default configuration
Reset scheme (BORAXpress)
Reset scheme and voltage monitoring
+11
File:Borax-reset-scheme.png
no edit summary
System boot and recovery via microSD card (BELK/BXELK)
How to configure the system for microSD boot
-897
Creating and building example Vivado project (BELK/BXELK)
no edit summary
+19
3 November 2015
Integration guide (Bora/BoraX/BoraLite)
PS' I²C buses
+20
Programmable logic (Bora)
no edit summary
+56
Integration guide (Bora/BoraX/BoraLite)
no edit summary
-21,710
Programmable logic (Bora)
no edit summary
-12
Programmable logic (Bora)
no edit summary
+3,768
Programmable logic (Bora)
FPGA Bank 35
+18,199
Programmable logic (Bora)
FPGA Bank 34
+5,576
Integration guide (Bora/BoraX/BoraLite)
PL bank 34
-5,669
Pinout (BORAXpress)
J3 even pins (2 to 140)
+36
Pinout (BORAXpress)
J3 even pins (2 to 140)
+9,045
Pinout (BORAXpress)
J3 odd pins (1 to 139)
+54
Pinout (BORAXpress)
J3 odd pins (1 to 139)
+5,463