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→J3 even pins (2 to 140)
==J3 even pins (2 to 140)==
{| class="wikitable" {| {{table}}
| align="center" style="background:#f0f0f0;"|'''Pin'''
| align="center" style="background:#f0f0f0;"|'''Pin Name'''
| align="center" style="background:#f0f0f0;"|'''Internal Connections'''
| align="center" style="background:#f0f0f0;"|'''Ball/pin #'''
| align="center" style="background:#f0f0f0;"|'''Supply Group'''
| align="center" style="background:#f0f0f0;"|'''Type'''
| align="center" style="background:#f0f0f0;"|'''Voltage'''
| align="center" style="background:#f0f0f0;"|'''Note'''
|-
| J3.2||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.4||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.6||MGTREFCLK1N||FPGA.MGTREFCLK1N_112||V5||MGTAVCC||D||||
|-
| J3.8||MGTREFCLK1P||FPGA.MGTREFCLK1P_112||U5||MGTAVCC||D||||
|-
| J3.10||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.12||MGTxRXP0||FPGA.MGTXRXP0_112||AA7||MGTAVCC||D||||
|-
| J3.14||MGTxRXN0||FPGA.MGTXRXN0_112||AB7||MGTAVCC||D||||
|-
| J3.16||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.18||MGTxRXP1||FPGA.MGTXRXP1_112||W8||MGTAVCC||D||||
|-
| J3.20||MGTxRXN1||FPGA.MGTXRXN1_112||Y8||MGTAVCC||D||||
|-
| J3.22||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.24||MGTxRXP2||FPGA.MGTXRXP2_112||AA9||MGTAVCC||D||||
|-
| J3.26||MGTxRXN2||FPGA.MGTXRXN2_112||AB9||MGTAVCC||D||||
|-
| J3.28||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.30||MGTxRXP3||FPGA.MGTXRXP3_112||W6||MGTAVCC||D||||
|-
| J3.32||MGTxRXN3||FPGA.MGTXRXN3_112||Y6||MGTAVCC||D||||
|-
| J3.34||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.36||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.38||IO_L24P_T3_13||FPGA.IO_L24P_T3_13||W17||Bank 13||I/O||User defined||
|-
| J3.40||IO_L24N_T3_13||FPGA.IO_L24N_T3_13||Y17||Bank 13||I/O||User defined||
|-
| J3.42||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.44||IO_L10P_T1_13||FPGA.IO_L10P_T1_13||Y12||Bank 13||I/O||User defined||
|-
| J3.46||IO_L10N_T1_13||FPGA.IO_L10N_T1_13||Y13||Bank 13||I/O||User defined||
|-
| J3.48||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.50||IO_L8P_T1_13||FPGA.IO_L8P_T1_13||AA12||Bank 13||I/O||User defined||
|-
| J3.52||IO_L8N_T1_13||FPGA.IO_L8N_T1_13||AB12||Bank 13||I/O||User defined||
|-
| J3.54||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.56||IO_L6P_T0_13||FPGA.IO_L6P_T0_13||U13||Bank 13||I/O||User defined||
|-
| J3.58||IO_L6N_T0_VREF_13||FPGA.IO_L6N_T0_VREF_13||U14||Bank 13||I/O||User defined||
|-
| J3.60||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.62||MON_MGTAVCC||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| J3.64||MON_MGTAVCCAUX||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| J3.66||MON_MGTAVTT||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| J3.68||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.70||RFU||-||-||-||-||-||Reserved for future use. Must be left floating.
|-
| J3.72||MON_VCCPLL||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| J3.74||MON_XADC_VCC||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| J3.76||MON_FPGA_VDDIO_BANK35||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| J3.78||MON_FPGA_VDDIO_BANK34||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| J3.80||MON_FPGA_VDDIO_BANK13||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| J3.82||MON_1.8V_IO||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| J3.84||MON_3.3V||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| J3.86||MON_1V2_ETH||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| J3.88||MON_VDDQ_1V5||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| J3.90||MON_1.8V||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| J3.92||MON_1.0V||||||||A||||By default this pin must not be connected. Optionally it can route power voltage generated by BoraXpress PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| J3.94||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.96||VDDIO_BANK13||FPGA.VCCO_13||AA13
AB20
T18
Y16
W19
V12
U15||Bank 13||S||User defined||Bank13 I/O Power Supply
|-
| J3.98||VDDIO_BANK13||FPGA.VCCO_13||AA13
AB20
T18
Y16
W19
V12
U15||Bank 13||S||User defined||Bank13 I/O Power Supply
|-
| J3.100||RFU||-||-||-||-||-||Reserved for future use. Must be left floating.
|-
| J3.102||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.104||IO_L22P_T3_13||FPGA.IO_L22P_T3_13||U17||Bank 13||I/O||User defined||
|-
| J3.106||IO_L22N_T3_13||FPGA.IO_L22N_T3_13||U18||Bank 13||I/O||User defined||
|-
| J3.108||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.110||IO_L20P_T3_13||FPGA.IO_L20P_T3_13||U19||Bank 13||I/O||User defined||
|-
| J3.112||IO_L20N_T3_13||FPGA.IO_L20N_T3_13||V19||Bank 13||I/O||User defined||
|-
| J3.114||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.116||IO_L17P_T2_13||FPGA.IO_L17P_T2_13||AB16||Bank 13||I/O||User defined||
|-
| J3.118||IO_L17N_T2_13||FPGA.IO_L17N_T2_13||AB17||Bank 13||I/O||User defined||
|-
| J3.120||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.122||IO_L15P_T2_DQS_13||FPGA.IO_L15P_T2_DQS_13||AB21||Bank 13||I/O||User defined||
|-
| J3.124||IO_L15N_T2_DQS_13||FPGA.IO_L15N_T2_DQS_13||AB22||Bank 13||I/O||User defined||
|-
| J3.126||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.128||IO_L13P_T2_MRCC_13||FPGA.IO_L13P_T2_MRCC_13||Y18||Bank 13||I/O||User defined||
|-
| J3.130||IO_L13N_T2_MRCC_13||FPGA.IO_L13N_T2_MRCC_13||Y19||Bank 13||I/O||User defined||
|-
| J3.132||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.134||IO_L11P_T1_SRCC_13||FPGA.IO_L11P_T1_SRCC_13||AA14||Bank 13||I/O||User defined||
|-
| J3.136||IO_L11N_T1_SRCC_13||FPGA.IO_L11N_T1_SRCC_13||AA15||Bank 13||I/O||User defined||
|-
| J3.138||DGND||DGND||-||-||G||-||Digital ground
|-
| J3.140||DGND||DGND||-||-||G||-||Digital ground
|}
