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→FPGA Bank 35
On Bora side, routing of bank 35 has been optimized to interface 16-bit DDR3 SDRAM memory devices, clocked at a maximum frequency of 400 MHz. Regarding power voltage, Bank 35 is configurable and must be powered by carrier board. Please note that some signals belonging to this bank can be configured alternatively as XADC auxiliary analog inputs. For routing details, please refer to [[Integration_guide_(Bora)#PL_bank_35 | PL Bank 35 routing]].
===Routing information===
On Bora side, routing of bank 35 has been optimized to interface 16-bit DDR3 SDRAM memory devices, clocked at a maximum frequency of 400 MHz.
Signals have been grouped in the following classes:
* FDDR_ADDR
* FDDR_CK
* FDDR_BYTE0
* FDDR_BYTE1
Some of them are differential pairs. These kind of signals are highlighted in dark grey in the following sections where, for each signal, detailed information are provided, related to routing rules implemented on Bora SoM and carrier board guidelines.
Following tables indicates general recommended rules for single-ended and differantial pairs on carrier board in terms of impedence and isolation.
Differential pairs:
{| class="wikitable" border="1"
| align="center" style="background:#f0f0f0;"|''' '''
| align="center" style="background:#f0f0f0;"|''' Value '''
| align="center" style="background:#f0f0f0;"|''' UOM '''
|-
| Common Mode impedance typ||align="center"|55||align="center"|Ohm
|-
| Differential Mode impedance typ||align="center"|100||align="center"|Ohm
|-
| Isolation||align="center"|4x||align="center"|gap
|-
|}
Single-ended signals:
{| class="wikitable" border="1"
| align="center" style="background:#f0f0f0;"|''' '''
| align="center" style="background:#f0f0f0;"|''' Value '''
| align="center" style="background:#f0f0f0;"|''' UOM '''
|-
| Common Mode impedance typ||align="center"|55||align="center"|Ohm
|-
| Isolation||align="center"|2x||align="center"|width
|-
|}
About power voltage, Bank 35 is configurable and must be powered by carrier board.
Please note that some signals belonging to this bank can be configured alternatively as XADC auxiliary analog
inputs.
===== FDDR_ADDR class =====
Following table details routing rules implemented on Bora SoM and suggested carrier board guidelines for FDDR_ADDR class signals. The picture shows connection scheme and the nomenclature used in the table.
[[File:FDDR_ADDR.png]]
{| class="wikitable" border="1"
! align="center" style="background:#f0f0f0;" rowspan="2" | '''Bora pin name'''
! align="center" style="background:#f0f0f0;" rowspan="2" | '''Group name'''
! align="center" style="background:#f0f0f0;" rowspan="2" | '''Carrier board net name'''
! align="center" style="background:#f0f0f0;" colspan="3" | '''SoM routing rules and specifications'''
! align="center" style="background:#f0f0f0;" colspan="6" | '''Carrier board guidelines'''
|-
! align="center" style="background:#f0f0f0;" | '''Actual length<br>[mils]'''
! align="center" style="background:#f0f0f0;" | '''Max length match<br>[mils]'''
! align="center" style="background:#f0f0f0;" | '''Nominal max length<br>[mils]'''
! align="center" style="background:#f0f0f0;" | '''AD_A2 length match<br>[mils]'''
! align="center" style="background:#f0f0f0;" | '''AD_AT length match<br>[mils]'''
! align="center" style="background:#f0f0f0;" | '''AD_AS1 length match<br>[mils]'''
! align="center" style="background:#f0f0f0;" | '''AD_AS1 max length<br>[mils]'''
! align="center" style="background:#f0f0f0;" | '''AD_AT max length<br>[mils]'''
! align="center" style="background:#f0f0f0;" | '''AD_A2+AD_AS1 max length<br>[mils]'''
|-
|IO_L17N_T2_AD5N_35||FDDR_ADDR||FDDR_ADDR_3||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
|-
| IO_L20P_T3_AD6P_35||FDDR_ADDR||FDDR_BA_2||align="center"|1853,4||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
|-
| IO_L16N_T2_35||FDDR_ADDR||FDDR_ADDR_5||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
|-
| IO_L18N_T2_AD13N_35||FDDR_ADDR||FDDR_ADDR_1||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
|-
| IO_L24N_T3_AD15N_35||FDDR_ADDR||FDDR_CKE_0||align="center"|1834,3||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
|-
| IO_L23P_T3_35||FDDR_ADDR||FDDR_CAS_N||align="center"|1857,01||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
|-
| IO_L14N_T2_AD4N_SRCC_35||FDDR_ADDR||FDDR_ADDR_9||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
|-
| IO_L24P_T3_AD15P_35||FDDR_ADDR||FDDR_CS0_N||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
|-
| IO_L14P_T2_AD4P_SRCC_35||FDDR_ADDR||FDDR_ADDR_10||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
|-
| IO_L15P_T2_DQS_AD12P_35||FDDR_ADDR||FDDR_ADDR_8||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
|-
| IO_L15N_T2_DQS_AD12N_35||FDDR_ADDR||FDDR_ADDR_7||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
|-
| IO_L12N_T1_MRCC_35||FDDR_ADDR||FDDR_RESET_N||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
|-
| IO_L13P_T2_MRCC_35||FDDR_ADDR||FDDR_ADDR_12||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
|-
| IO_L13N_T2_MRCC_35||FDDR_ADDR||FDDR_ADDR_11||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
|-
| IO_25_35||FDDR_ADDR||FDDR_ODT_0||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
|-
| IO_L23N_T3_35||FDDR_ADDR||FDDR_WE_N||align="center"|1869,66||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
|-
| IO_L17P_T2_AD5P_35||FDDR_ADDR||FDDR_ADDR_4||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
|-
| IO_L22N_T3_AD7N_35||FDDR_ADDR||FDDR_RAS_N||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
|-
| IO_L20N_T3_AD6N_35||FDDR_ADDR||FDDR_BA_1||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
|-
| IO_L18P_T2_AD13P_35||FDDR_ADDR||FDDR_ADDR_2||align="center"|1853,7||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
|-
| IO_L16P_T2_35||FDDR_ADDR||FDDR_ADDR_6||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
|-
| IO_L22P_T3_AD7P_35||FDDR_ADDR||FDDR_BA_0||align="center"|1850,82||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
|-
| IO_L19P_T3_35||FDDR_ADDR||FDDR_ADDR_0||align="center"|1836,73||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
|-
|}
===== FDDR_CK class =====
Following table details routing rules implemented on Bora SoM and suggested carrier board guidelines for FDDR_CK class signals. The picture shows connection scheme and the nomenclature used in the table.
[[File:FDDR_CK.png]]
{| class="wikitable" border="1"
! align="center" style="background:#f0f0f0;" rowspan="2" |'''Bora pin name'''
! align="center" style="background:#f0f0f0;" rowspan="2" |'''Group name'''
! align="center" style="background:#f0f0f0;" rowspan="2" |'''Carrier board net name'''
! align="center" style="background:#f0f0f0;" colspan="4" |'''SoM routing rules and specifications'''
! align="center" style="background:#f0f0f0;" colspan="8" |'''Carrier board guidelines'''
|-
! align="center" style="background:#f0f0f0;"|'''Actual length<br>[mils]'''
! align="center" style="background:#f0f0f0;"|'''Intra-pair match<br>[mils]'''
! align="center" style="background:#f0f0f0;"|'''Max length match (with respect to FDDR_ADDR group)<br>[mils]'''
! align="center" style="background:#f0f0f0;"|'''Nominal max length<br>[mils]'''
! align="center" style="background:#f0f0f0;"|'''Intra-pair match<br>[mils]'''
! align="center" style="background:#f0f0f0;"|'''CK_A2 pair match (with respect to FDDR_ADDR)<br>[mils]'''
! align="center" style="background:#f0f0f0;"|'''CK_AT intra-pair match<br>[mils]'''
! align="center" style="background:#f0f0f0;"|'''CK_AS1 match (with respect to FDDR_ADDR)<br>[mils]'''
! align="center" style="background:#f0f0f0;"|'''CK_AS1 max length<br>[mils]'''
! align="center" style="background:#f0f0f0;"|'''CK_AT maximum length<br>[mils]'''
! align="center" style="background:#f0f0f0;"|'''CK_AT pair match (with respect to FDDR_ADDR)<br>[mils]'''
! align="center" style="background:#f0f0f0;"|'''CK_A2+CK_AS1 max length<br>[mils]'''
|- style="background: gray"
| IO_L21P_T3_DQS_AD14P_35||FDDR_CK||FDDR_CK_P0||align="center"|1900,39||align="center"|5||align="center"|80||align="center"|1912||align="center"|10||align="center"|40||align="center"|5||align="center"|50||align="center"|60||align="center"|400||align="center"|100||align="center"|2100
|- style="background: gray"
| IO_L21N_T3_DQS_AD14N_35||FDDR_CK||FDDR_CK_N0||align="center"|1898,17||align="center"|5||align="center"|80||align="center"|1912||align="center"|10||align="center"|40||align="center"|5||align="center"|50||align="center"|60||align="center"|400||align="center"|100||align="center"|2100
|-
|}
===== FDDR_BYTE0 class =====
Following table details routing rules implemented on Bora SoM and suggested carrier board guidelines for FDDR_BYTE0 class signals.
{| class="wikitable" border="1"
! align="center" style="background:#f0f0f0;" rowspan="2" |'''Pin Name'''
! align="center" style="background:#f0f0f0;" rowspan="2" |'''Group name'''
! align="center" style="background:#f0f0f0;" rowspan="2" |'''Carrier board net name'''
! align="center" style="background:#f0f0f0;" colspan="4" |'''SoM routing rules and specifications'''
! align="center" style="background:#f0f0f0;" colspan="3" |'''Carrier board guidelines'''
|-
! align="center" style="background:#f0f0f0;"|'''Actual length<br>[mils]'''
! align="center" style="background:#f0f0f0;"|'''Max length match<br>[mils]'''
! align="center" style="background:#f0f0f0;"|'''Max inter-pair match length on SOM<br>[mils]'''
! align="center" style="background:#f0f0f0;"|'''Nominal max length<br>[mils]'''
! align="center" style="background:#f0f0f0;"|'''Group match (mandatory)<br>[mils]'''
! align="center" style="background:#f0f0f0;"|'''Intra-pair match (mandatory)<br>[mils]'''
! align="center" style="background:#f0f0f0;"|'''Max length<br>[mils]'''
|-
| IO_L2N_T0_AD8N_35||FDDR_BYTE0||FDDR_DQ_2||align="center"|1222,66||align="center"|15||align="center"|-||align="center"|1230||align="center"|25||align="center"|-||align="center"|CK_A2+CK_AS1(max)
|-
| IO_L6P_T0_35||FDDR_BYTE0||FDDR_DQ_7||align="center"|1219,68||align="center"|15||align="center"|-||align="center"|1230||align="center"|25||align="center"|-||align="center"|CK_A2+CK_AS1(max)
|-
| IO_L5P_T0_AD9P_35||FDDR_BYTE0||FDDR_DQ_5||align="center"|1226,42||align="center"|15||align="center"|-||align="center"|1230||align="center"|25||align="center"|-||align="center"|CK_A2+CK_AS1(max)
|-
| IO_L4P_T0_35||FDDR_BYTE0||FDDR_DQ_3||align="center"|1219,68||align="center"|15||align="center"|-||align="center"|1230||align="center"|25||align="center"|-||align="center"|CK_A2+CK_AS1(max)
|-
| IO_L2P_T0_AD8P_35||FDDR_BYTE0||FDDR_DQ_1||align="center"|1219,68||align="center"|15||align="center"|-||align="center"|1230||align="center"|25||align="center"|-||align="center"|CK_A2+CK_AS1(max)
|-
| IO_L1N_T0_AD0N_35||FDDR_BYTE0||FDDR_DQ_0||align="center"|1219,68||align="center"|15||align="center"|-||align="center"|1230||align="center"|25||align="center"|-||align="center"|CK_A2+CK_AS1(max)
|-
| IO_L4N_T0_35||FDDR_BYTE0||FDDR_DQ_4||align="center"|1219,68||align="center"|15||align="center"|-||align="center"|1230||align="center"|25||align="center"|-||align="center"|CK_A2+CK_AS1(max)
|-
| IO_L5N_T0_AD9N_35||FDDR_BYTE0||FDDR_DQ_6||align="center"|1219,68||align="center"|15||align="center"|-||align="center"|1230||align="center"|25||align="center"|-||align="center"|CK_A2+CK_AS1(max)
|-
| IO_L1P_T0_AD0P_35||FDDR_BYTE0||FDDR_DM_0||align="center"|1219,68||align="center"|15||align="center"|-||align="center"|1230||align="center"|25||align="center"|-||align="center"|CK_A2+CK_AS1(max)
|- style="background: gray"
| IO_L3P_T0_DQS_AD1P_35||FDDR_BYTE0||FDDR_DQS_P0||align="center"|1221,04||align="center"|15||align="center"|5||align="center"|1230||align="center"|25||align="center"|5||align="center"|CK_A2+CK_AS1(max)
|- style="background: gray"
| IO_L3N_T0_DQS_AD1N_35||FDDR_BYTE0||FDDR_DQS_N0||align="center"|1219,42||align="center"|15||align="center"|5||align="center"|1230||align="center"|25||align="center"|5||align="center"|CK_A2+CK_AS1(max)
|-
|}
===== FDDR_BYTE1 class =====
Following table details routing rules implemented on Bora SoM and suggested carrier board guidelines for FDDR_BYTE1 class signals.
{| class="wikitable" border="1"
! align="center" style="background:#f0f0f0;" rowspan="2" |'''Pin Name'''
! align="center" style="background:#f0f0f0;" rowspan="2" |'''Group name'''
! align="center" style="background:#f0f0f0;" rowspan="2" |'''Carrier board net name'''
! align="center" style="background:#f0f0f0;" colspan="4" |'''SoM routing rules and specifications'''
! align="center" style="background:#f0f0f0;" colspan="3" |'''Carrier board guidelines'''
|-
! align="center" style="background:#f0f0f0;"|'''Actual length<br>[mils]'''
! align="center" style="background:#f0f0f0;"|'''Max length match<br>[mils]'''
! align="center" style="background:#f0f0f0;"|'''Max inter-pair match length on SOM<br>[mils]'''
! align="center" style="background:#f0f0f0;"|'''Nominal max length<br>[mils]'''
! align="center" style="background:#f0f0f0;"|'''Group match (mandatory)<br>[mils]'''
! align="center" style="background:#f0f0f0;"|'''Intra-pair match (mandatory)<br>[mils]'''
! align="center" style="background:#f0f0f0;"|'''Max length<br>[mils]'''
|-
| IO_L10N_T1_AD11N_35||FDDR_BYTE1||FDDR_DQ_12||align="center"|1345,93||align="center"|15||align="center"|-||align="center"|1355||align="center"|20||align="center"|-||align="center"|CK_A2+CK_AS1(max)
|-
| IO_L10P_T1_AD11P_35||FDDR_BYTE1||FDDR_DQ_11||align="center"|1345,93||align="center"|15||align="center"|-||align="center"|1355||align="center"|20||align="center"|-||align="center"|CK_A2+CK_AS1(max)
|-
| IO_L11P_T1_SRCC_35||FDDR_BYTE1||FDDR_DQ_13||align="center"|1353,43||align="center"|15||align="center"|-||align="center"|1355||align="center"|20||align="center"|-||align="center"|CK_A2+CK_AS1(max)
|-
| IO_L12P_T1_MRCC_35||FDDR_BYTE1||FDDR_DQ_15||align="center"|1341,3||align="center"|15||align="center"|-||align="center"|1355||align="center"|20||align="center"|-||align="center"|CK_A2+CK_AS1(max)
|-
| IO_L11N_T1_SRCC_35||FDDR_BYTE1||FDDR_DQ_14||align="center"|1340||align="center"|15||align="center"|-||align="center"|1355||align="center"|20||align="center"|-||align="center"|CK_A2+CK_AS1(max)
|-
| IO_L8P_T1_AD10P_35||FDDR_BYTE1||FDDR_DQ_9||align="center"|1340||align="center"|15||align="center"|-||align="center"|1355||align="center"|20||align="center"|-||align="center"|CK_A2+CK_AS1(max)
|-
| IO_L7N_T1_AD2N_35||FDDR_BYTE1||FDDR_DQ_8||align="center"|1340||align="center"|15||align="center"|-||align="center"|1355||align="center"|20||align="center"|-||align="center"|CK_A2+CK_AS1(max)
|-
| IO_L8N_T1_AD10N_35||FDDR_BYTE1||FDDR_DQ_10||align="center"|1340||align="center"|15||align="center"|-||align="center"|1355||align="center"|20||align="center"|-||align="center"|CK_A2+CK_AS1(max)
|-
| IO_L7P_T1_AD2P_35||FDDR_BYTE1||FDDR_DM_1||align="center"|1345,93||align="center"|15||align="center"|-||align="center"|1355||align="center"|20||align="center"|-||align="center"|CK_A2+CK_AS1(max)
|- style="background: gray"
| IO_L9P_T1_DQS_AD3P_35||FDDR_BYTE1||FDDR_DQS_P1||align="center"|1354,26||align="center"|15||align="center"|5||align="center"|1355||align="center"|20||align="center"|5||align="center"|CK_A2+CK_AS1(max)
|- style="background: gray"
| IO_L9N_T1_DQS_AD3N_35||FDDR_BYTE1||FDDR_DQS_N1||align="center"|1350,66||align="center"|15||align="center"|5||align="center"|1355||align="center"|20||align="center"|5||align="center"|CK_A2+CK_AS1(max)
|-
|}
===== VREF =====
Recommendations:
* use a "T" connection as shown by following picture
* use 20+ mils trace
* place bypass capacitors as close as possible to power balls.
[[File:VREF.png]]
===== Related Xilinx documentation =====
* [http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_0/ug586_7Series_MIS.pdf Xilinx Memory Interface Solutions UG586]
* [http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_0/ds176_7Series_MIS.pdf Xilinx Memory Interface Solutions Data Sheet]
== FPGA Bank 13 (Zynq 7020 only) ==
