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Reset scheme (Naon)

Revision as of 14:06, 2 May 2012 by DevWikiAdmin (talk | contribs)

Info Box
Naon am387x-dm814x.png Applies to Naon

Contents

Accessible reset signalsEdit

Five different signals are provided by Naon SOM. FOllowing sections describes in more detail each one.

MRST (J2.102)Edit

This pin is connected to HDRST signal (cold reset) of PMIC TPS659113. When high, this signals keeps PMIC in off mode and resets TPS659113 to default settings. MRST has a weak internal pulldown.

PORSTn (J2.109)Edit

PORSTn is a bidirectional open-drain signal. It is connected to:

  • PORn input (Power-on Reset) of DM8148 processor
  • output of voltage monitor ([#Voltage monitor])
  • NRESPWRON2 output of PMIC.

Internal pullup is 10kOhm.

RSTOUTn (J2.91)Edit

This signal is asserted by DM8148 processor until it gets out of reset. It is usually used to reset external memories and peripherals conneteced to processor. It is connected to:

  • RSTOUT_WD_OUTn pad of DM8148 processor
  • peripherals and memories.

In case it is used to reset devices on carrier board, its driving capability has to be taken into account.

CPU_RESETn (J2.15)Edit

External Warm Reset

JTAG_TRSTn (J2.100)Edit

Emulation Warm Reset

Voltage monitorEdit