Reset scheme (Naon)
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Contents
Accessible reset signals[edit | edit source]
Five different signals are provided by Naon SOM. Following sections describe in more detail each one.
MRST (J2.102)[edit | edit source]
This pin is connected to HDRST signal (cold reset) of PMIC TPS659113. When high, this signals keeps PMIC in off mode and resets TPS659113 to default settings. MRST has a weak internal pulldown.
PORSTn (J2.109)[edit | edit source]
PORSTn is a bidirectional open-drain signal. It is connected to:
- PORn input (Power-on Reset) of DM8148 processor
- output of voltage monitor (see Reset scheme (Naon)#Voltage monitor)
- NRESPWRON2 output of PMIC.
Internal pullup is 10kOhm.
RSTOUTn (J2.91)[edit | edit source]
This ouput signal is asserted by DM8148 processor until it gets out of reset. It is usually used to reset external memories and peripherals conneteced to processor. It is connected to:
- RSTOUT_WD_OUTn pad of DM8148 processor
- 2k2 pull down resistor
- peripherals and memories.
In case it is used to reset devices on carrier board, its driving capability has to be taken into account.
CPU_RESETn (J2.15)[edit | edit source]
This input signal acts as External Warm Reset. It is connected to processor's RESETn pad. Internal pullup is 2.2kOhm.
JTAG_TRSTn (J2.100)[edit | edit source]
This input signal acts as Emulation Warm Reset. It is connected to processor's TRSTn pad. Internal pulldown is 4.7kOhm
Voltage monitor[edit | edit source]
Naon SOM is equipped with a multiple-input voltage monitor whose reset output is connected to PORSTn. Monitored voltage rails include 3.3V provided by carrier board.
