Bureaucrats, dave_user, Administrators
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* Video and night vision equipment
The processors in the PS always boot first, allowing a software centric approach for PL system boot and PL configuration. The PL can be configured as part of the boot process or configured at some point in the future. Additionally, the PL can be completely reconfigured or used with partial, dynamic reconfiguration (PR). PR allows configuration of a portion of the PL. This enables optional design changes such as updating coefficients or time-multiplexing of the PL resources by swapping in new algorithms as needed. Bora can mount two versions of the Zynq processor. The following table shows a comparison between the devicesprocessor models, highlighting the differences:
{| class="wikitable" |
| '''Size min'''||8 MB
|-
| '''Size max'''||64 16 MB
|-
| '''Chip select'''||SPI_CS0n
| '''Size min'''||128 MB
|-
| '''Size max'''||2 1 GB
|-
| '''Width'''||8 bit
|-
|}
== Power supply unit ==
Bora, as the other Ultra Line CPU modules, embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters. For detailed information, please refer to Section 5.1[[Power_(Bora)]].
== CPU module connectors ==
All interface signals Bora provides are routed through three 140 pin 0.6mm pitch stacking connectors (named J1, J2 and J3). The dedicated carrier board must mount the mating connectors and connect the desired peripheral interfaces according to Bora pinout specifications.
