Difference between revisions of "PL initialization signals (Bora/BoraX/BoraLite)"
(Tag: Visual edit) |
|||
| (11 intermediate revisions by 3 users not shown) | |||
| Line 5: | Line 5: | ||
{{InfoBoxBottom}} | {{InfoBoxBottom}} | ||
| − | + | __FORCETOC__ | |
| − | + | <section begin=PL/> | |
| − | = PL Logic | + | ==PL initialization signals == |
| + | This page provides information about the Programmable Logic (PL) initialization signals: PROGRAM_B, INIT_B, and DONE. | ||
Please refer to [https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf#page=218 Zynq Technical Reference Manual UG-585] for more information about usage and configuration of initialization circuit and signals. | Please refer to [https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf#page=218 Zynq Technical Reference Manual UG-585] for more information about usage and configuration of initialization circuit and signals. | ||
| − | As | + | As described in ''Table 6-24: PL Initialization Signals'' of ''Zynq-7000 SoC Technical Reference Manual (UG585)'', the user can initialize the PL using these signals. |
BORA, BORAX, and BORALite SOM are configured in the following way: | BORA, BORAX, and BORALite SOM are configured in the following way: | ||
| − | |||
* PROGRAM_B has an internal 10kΩ pull-up to VCCO_0 as indicated on Xilinx [https://www.xilinx.com/support/answers/56272.html AR#56272] | * PROGRAM_B has an internal 10kΩ pull-up to VCCO_0 as indicated on Xilinx [https://www.xilinx.com/support/answers/56272.html AR#56272] | ||
* INIT_B has no pull-up/down | * INIT_B has no pull-up/down | ||
| − | * DONE has no pull-up/down. It does not require | + | * DONE has no pull-up/down. It does not require any external pull-up or pull-down but can be used for connecting a user led for a configuration completed indication (see for example [https://mirror.dave.eu/bora/hw/BoraXEVB/S-EVBBX0000C0R-1.6.1_color.pdf#page=4 BoraXEVB schematics]). |
| − | = External pull-ups = | + | === External pull-ups === |
| − | * PROGRAM_B: | + | * PROGRAM_B: UG-585 indicates to use a 4.7kΩ pull-up resistor for this signal. This value was not known when the Xilinx Zynq 7000 family was released. Nevertheless, to date, no issues have been reported although this pull-up is a little bit weaker. In any case, an external pull-up to a 3.3V controlled power domain can be put in parallel with the internal 10kΩ resistor to get a stronger pull-up. For more details, please contact [mailto:helpdesk@dave.eu the technical support]. |
* INIT_B: for using this signal as ''PL initializing signal Low-to-High transition'', place an external pull-up to a 3.3V controlled power domain. | * INIT_B: for using this signal as ''PL initializing signal Low-to-High transition'', place an external pull-up to a 3.3V controlled power domain. | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | + | <section end=PL/> | |
Latest revision as of 15:18, 11 January 2024
| HOME | SOMs | SBCs | ToloMEO Embedded Assistant |  GET A QUOTE
|
 ONLINE HELPDESK
|
| Roadmap | IoT Services | ML/AI services | Embedded Design Services |
Info Box
|
PL initialization signals[edit | edit source]
This page provides information about the Programmable Logic (PL) initialization signals: PROGRAM_B, INIT_B, and DONE.
Please refer to Zynq Technical Reference Manual UG-585 for more information about usage and configuration of initialization circuit and signals.
As described in Table 6-24: PL Initialization Signals of Zynq-7000 SoC Technical Reference Manual (UG585), the user can initialize the PL using these signals.
BORA, BORAX, and BORALite SOM are configured in the following way:
- PROGRAM_B has an internal 10kΩ pull-up to VCCO_0 as indicated on Xilinx AR#56272
- INIT_B has no pull-up/down
- DONE has no pull-up/down. It does not require any external pull-up or pull-down but can be used for connecting a user led for a configuration completed indication (see for example BoraXEVB schematics).
External pull-ups[edit | edit source]
- PROGRAM_B: UG-585 indicates to use a 4.7kΩ pull-up resistor for this signal. This value was not known when the Xilinx Zynq 7000 family was released. Nevertheless, to date, no issues have been reported although this pull-up is a little bit weaker. In any case, an external pull-up to a 3.3V controlled power domain can be put in parallel with the internal 10kΩ resistor to get a stronger pull-up. For more details, please contact the technical support.
- INIT_B: for using this signal as PL initializing signal Low-to-High transition, place an external pull-up to a 3.3V controlled power domain.
