Bureaucrats, dave_user, Administrators
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→Handling CPU-initiated software reset
For these reasons, it is strongly recommended to use a different approach that, in combination with the use of a processor's watchdog timer (WDT), provides a full hardware reset in case a software reset is issued.
This technique is implemented in [[ORCA_SOM/DESK-MX8M-L | DESK-MX8M-L]]. At software level, U-Boot and Linux kernel software reset routines make use of processor's WDT to assert the WDOG1_WDOG_B reset signal. This signal in turn is routed to GPIO1_IO02 pad (MUX mode = 1, ''internal connection only''). At hardware level, this signal is connected to the PMIC WDOG_B input that generates a system POR.
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[[Category:ORCA]]
