Changes

This Two different routing options are available for this pin is routed by default to the PMIC_ON_REQ internal signal. It can be optionally routed to the voltage monitor master reset to issue a reset without involving the PMIC.

By default, this pin is connected to PMIC's PMIC_ON_REQ signal. The PMIC_ON_REQ signal is driven by iMX8MPlus SoC to place the system in power -down mode. Optionally, PMIC_ON_REQ//VMON_RST can be routed to the master reset input of a voltage supervisor instead. For more details about this option, please write to the [mailto:sales@dave.eu Sales Department].

 {| style="color:#000000; border:solid 2px #73B2C7; background-color:#ededed;font-size:95%; vertical-align:middle;"| [[File:TBD.png|30px]]| '''Section not completed yet'''|}  '''By default, MX8 processor does not assert any external signal when it initiates ORCA SOM implements a conservative approach regarding CPU-initiated software reset sequence. Also default In essence, whenever a software reset implementation does not guarantee that all processor registers are reset properly'''.  For these reasons, it is strongly recommended to use a different approach thatissued, in combination with the use of a processor's watchdog timer (WDT), provides a full hardware reset in case a software reset power-up cycle is issuedtriggered. This technique is implemented in [[ORCA_SOM/DESK-MX8M-L | DESK-MX8M-L]]. At the software level, U-Boot and Linux kernel software reset routines make use of processora SOC's WDT to assert the WDOG1_WDOG_B reset signal. This signal in turn is routed to GPIO1_IO02 pad (MUX mode = 1, ''internal connection only''). At the hardware level, this signal is connected to the PMIC WDOG_B input that generates a system PORto achieve the desired outcome.