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→Handling CPU-initiated software reset
=== Handling CPU-initiated software reset ===
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| '''Section not completed yet'''
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'''By default, MX8 processor does not assert any external signal when it initiates a software reset sequence. Also default software reset implementation does not guarantee that all processor registers are reset properly'''.
For these reasons, it is strongly recommended to use a different approach that, in combination with the use of a processor's watchdog timer (WDT), provides a full hardware reset in case a software reset is issued.
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[[Category:ORCA]]
