Difference between revisions of "ORCA SOM/ORCA Hardware/Power and Reset/Power Supply Unit (PSU) and recommended power-up sequence"
< ORCA SOM | ORCA Hardware
(Created page with "{{subst:Power_sequence | nome-som=ORCA | kit-code=MX8}}") |
|||
| (3 intermediate revisions by 2 users not shown) | |||
| Line 1: | Line 1: | ||
| − | <section begin=History/> | + | <section begin="History" /> |
{| style="border-collapse:collapse; " | {| style="border-collapse:collapse; " | ||
| − | !colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History | + | ! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History |
|- | |- | ||
| − | + | ! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date | |
| − | !style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date | + | ! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes |
| − | !style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes | ||
|- | |- | ||
| − | |style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"| | + | | style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |2021/02/03 |
| − | |style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"| | + | | style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release |
| − | |||
|- | |- | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
|- | |- | ||
|} | |} | ||
| − | <section end=History/> | + | <section end="History" /> |
| − | <section begin=Body/> | + | <section begin="Body" /> |
== Power Supply Unit (PSU) and recommended power-up sequence == | == Power Supply Unit (PSU) and recommended power-up sequence == | ||
| − | Implementing correct power-up sequence for '' | + | Implementing correct power-up sequence for ''iMX8MPlus'' processors is not a trivial task because several power rails are involved. |
ORCA SOM simplifies this task by embedding all the needed circuitry. The following picture shows a simplified block diagram of PSU/voltage monitoring circuitry: | ORCA SOM simplifies this task by embedding all the needed circuitry. The following picture shows a simplified block diagram of PSU/voltage monitoring circuitry: | ||
| Line 38: | Line 28: | ||
* generates the proper power-up sequence required by the SOC processor and surrounding memories and peripherals | * generates the proper power-up sequence required by the SOC processor and surrounding memories and peripherals | ||
* synchronizes the powering up of carrier board in order to prevent back power | * synchronizes the powering up of carrier board in order to prevent back power | ||
| − | |||
=== Power-up sequence=== | === Power-up sequence=== | ||
| − | + | The typical power-up sequence is the following: | |
| + | # 3.3VIN main power supply rail is powered | ||
| + | # SNVS domain signals are pulled-up (unless carrier board circuitry keeps this signal low for any reason) | ||
| + | # CPU_PORn (active-low) is driven low by PMIC | ||
| + | # RTC_RESET_B are internally released after 200ms | ||
| + | # PMIC initiates power-up sequence needed by iMX8M processor | ||
| + | # BOARD_PGOOD goes up when NVCC_3V3 (CPU I/O power rail) is ready | ||
| + | # CPU_PORn is deasserted after the last regulator to bring the processor out of reset | ||
==== Note on BOARD_PGOOD usage ==== | ==== Note on BOARD_PGOOD usage ==== | ||
| − | + | BOARD_PGOOD is generally used on carrier board to drive loads such as DC/DC enable inputs or switch on/off control signals. | |
| − | BOARD_PGOOD | + | Depending on the kind of such loads, BOARD_PGOOD might not be able to drive them properly because it has a 20mA output current absolute maximum rating. |
| − | + | In these cases a simple 2-input AND port with a level shifter for the PMIC_RST_B input can be used to address this issue. The following picture depicts a principle schematic showing this solution. | |
| − | + | SOM_VDD denotes the power rail used to power ORCA SoM (i.e. 3V3VIN). | |
[[File:ORCA-power-good.png]] | [[File:ORCA-power-good.png]] | ||
| − | + | Additionally, we suggest using ICs with Schmitt trigger input ports. | |
---- | ---- | ||
[[Category:ORCA]] | [[Category:ORCA]] | ||
Latest revision as of 18:26, 28 December 2023
| HOME | SOMs | SBCs | ToloMEO Embedded Assistant |  GET A QUOTE
|
 ONLINE HELPDESK
|
| Roadmap | IoT Services | ML/AI services | Embedded Design Services |
| History | |||
|---|---|---|---|
| Issue Date | Notes | ||
| 2021/02/03 | First release | ||
Power Supply Unit (PSU) and recommended power-up sequence[edit | edit source]
Implementing correct power-up sequence for iMX8MPlus processors is not a trivial task because several power rails are involved.
ORCA SOM simplifies this task by embedding all the needed circuitry. The following picture shows a simplified block diagram of PSU/voltage monitoring circuitry:
The PSU is composed of two main blocks:
- power management integrated circuit
- additional generic power management circuitry that completes PMIC functionalities
The PSU:
- generates the proper power-up sequence required by the SOC processor and surrounding memories and peripherals
- synchronizes the powering up of carrier board in order to prevent back power
Power-up sequence[edit | edit source]
The typical power-up sequence is the following:
- 3.3VIN main power supply rail is powered
- SNVS domain signals are pulled-up (unless carrier board circuitry keeps this signal low for any reason)
- CPU_PORn (active-low) is driven low by PMIC
- RTC_RESET_B are internally released after 200ms
- PMIC initiates power-up sequence needed by iMX8M processor
- BOARD_PGOOD goes up when NVCC_3V3 (CPU I/O power rail) is ready
- CPU_PORn is deasserted after the last regulator to bring the processor out of reset
Note on BOARD_PGOOD usage[edit | edit source]
BOARD_PGOOD is generally used on carrier board to drive loads such as DC/DC enable inputs or switch on/off control signals.
Depending on the kind of such loads, BOARD_PGOOD might not be able to drive them properly because it has a 20mA output current absolute maximum rating.
In these cases a simple 2-input AND port with a level shifter for the PMIC_RST_B input can be used to address this issue. The following picture depicts a principle schematic showing this solution.
SOM_VDD denotes the power rail used to power ORCA SoM (i.e. 3V3VIN).
Additionally, we suggest using ICs with Schmitt trigger input ports.
