Difference between revisions of "ORCA SOM/ORCA Hardware/Pinout Table"

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(Add alternate functions)
(Pinout WIP)
Line 65: Line 65:
 
* NAND.<x>: pin connected to the flash NAND
 
* NAND.<x>: pin connected to the flash NAND
 
* MTR: pin connected to voltage monitors
 
* MTR: pin connected to voltage monitors
 +
* TPM: pin connected to TPM unit <code>SE050</code>
 
|-
 
|-
 
|'''Ball/pin #'''  
 
|'''Ball/pin #'''  
Line 177: Line 178:
 
|J1.15
 
|J1.15
 
|CPU_ONOFF
 
|CPU_ONOFF
−
|TBD
+
|CPU.ONOFF
−
|TBD
+
|G22
−
|TBD
+
|NVCC_SNVS_1V8
−
|TBD
+
|I/O
−
|TBD
+
|internal pull-up 100k to NVCC_SNVS_1V8
 
|
 
|
 
|
 
|
Line 187: Line 188:
 
|J1.17
 
|J1.17
 
|CPU_PORn
 
|CPU_PORn
−
|TBD
+
|CPU.POR_B
−
|TBD
+
PMIC.POR_B
−
|TBD
+
|J29
−
|TBD
+
9
−
|TBD
+
|NVCC_SNVS_1V8
 +
|I/O
 +
|internal pull-up 100k to NVCC_SNVS_1V8
 
|
 
|
 
|
 
|
Line 198: Line 201:
 
|PMIC_ON_REQ
 
|PMIC_ON_REQ
 
//VMON_RST
 
//VMON_RST
−
|TBD
+
|CPU.PMIC_ON_REQ
−
|TBD
+
PMIC.PMIC_ON_REQ
−
|TBD
+
|F22
−
|TBD
+
39
−
|TBD
+
|NVCC_SNVS_1V8
 +
|I/O
 +
|optionally connected to
 +
voltage monitor reset
 
|
 
|
 
|
 
|
Line 208: Line 214:
 
|J1.21
 
|J1.21
 
|PMIC_RST_B
 
|PMIC_RST_B
−
|TBD
+
|PMIC.PMIC_RST_B
−
|TBD
+
|8
−
|TBD
+
|NVCC_SNVS_1V8
−
|TBD
+
|I/O
−
|TBD
+
|internal pull-up 100k to NVCC_SNVS_1V8
 
|
 
|
 
|
 
|
Line 218: Line 224:
 
|J1.23
 
|J1.23
 
|BOARD_PGOOD
 
|BOARD_PGOOD
−
|TBD
+
|MTR.RESET_B
−
|TBD
+
|2
−
|TBD
+
|NVCC_3V3
−
|TBD
+
|O
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 228: Line 234:
 
|J1.25
 
|J1.25
 
|BOOT_MODE0
 
|BOOT_MODE0
 +
|CPU.BOOT_MODE0
 +
|G10
 +
|NVCC_3V3
 
|TBD
 
|TBD
−
|TBD
+
|internal 10k pull-up or pull-down
−
|TBD
+
according to specific model
−
|TBD
 
−
|TBD
 
 
|
 
|
 
|
 
|
Line 238: Line 245:
 
|J1.27
 
|J1.27
 
|BOOT_MODE1
 
|BOOT_MODE1
 +
|CPU.BOOT_MODE1
 +
|F8
 +
|NVCC_3V3
 
|TBD
 
|TBD
−
|TBD
+
|internal 10k pull-up or pull-down
−
|TBD
+
according to specific model
−
|TBD
 
−
|TBD
 
 
|
 
|
 
|
 
|
Line 248: Line 256:
 
|J1.29
 
|J1.29
 
|BOOT_MODE2
 
|BOOT_MODE2
 +
|CPU.BOOT_MODE2
 +
|G8
 +
|NVCC_3V3
 
|TBD
 
|TBD
−
|TBD
+
|internal 10k pull-up or pull-down
−
|TBD
+
according to specific model
−
|TBD
 
−
|TBD
 
 
|
 
|
 
|
 
|
Line 268: Line 277:
 
|J1.33
 
|J1.33
 
|LVDS0_D3_N
 
|LVDS0_D3_N
−
|TBD
+
|CPU.LVDS0_D3_N
−
|TBD
+
|J28
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 278: Line 287:
 
|J1.35
 
|J1.35
 
|LVDS0_D3_P
 
|LVDS0_D3_P
−
|TBD
+
|CPU.LVDS0_D3_P
−
|TBD
+
|H29
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 288: Line 297:
 
|J1.37
 
|J1.37
 
|LVDS0_D2_N
 
|LVDS0_D2_N
−
|TBD
+
|CPU.LVDS0_D2_N
−
|TBD
+
|H28
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 298: Line 307:
 
|J1.39
 
|J1.39
 
|LVDS0_D2_P
 
|LVDS0_D2_P
−
|TBD
+
|CPU.LVDS0_D2_P
−
|TBD
+
|G29
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 308: Line 317:
 
|J1.41
 
|J1.41
 
|LVDS0_CLK_N
 
|LVDS0_CLK_N
−
|TBD
+
|CPU.LVDS0_CLK_N
−
|TBD
+
|G28
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 318: Line 327:
 
|J1.43
 
|J1.43
 
|LVDS0_CLK_P
 
|LVDS0_CLK_P
−
|TBD
+
|CPU.LVDS0_CLK_P
−
|TBD
+
|F29
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
−
|
+
|
 
|
 
|
 
|-
 
|-
 
|J1.45
 
|J1.45
 
|LVDS0_D1_N
 
|LVDS0_D1_N
−
|TBD
+
|CPU.LVDS0_D1_N
−
|TBD
+
|F28
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 338: Line 347:
 
|J1.47
 
|J1.47
 
|LVDS0_D1_P
 
|LVDS0_D1_P
−
|TBD
+
|CPU.LVDS0_D1_P
−
|TBD
+
|E29
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 348: Line 357:
 
|J1.49
 
|J1.49
 
|LVDS0_D0_N
 
|LVDS0_D0_N
−
|TBD
+
|CPU.LVDS0_D0_N
−
|TBD
+
|E28
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 358: Line 367:
 
|J1.51
 
|J1.51
 
|LVDS0_D0_P
 
|LVDS0_D0_P
−
|TBD
+
|CPU.LVDS0_D0_P
−
|TBD
+
|D29
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 378: Line 387:
 
|J1.55
 
|J1.55
 
|LVDS1_D3_N
 
|LVDS1_D3_N
−
|TBD
+
|CPU.LVDS1_D3_N
−
|TBD
+
|D28
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 388: Line 397:
 
|J1.57
 
|J1.57
 
|LVDS1_D3_P
 
|LVDS1_D3_P
−
|TBD
+
|CPU.LVDS1_D3_P
−
|TBD
+
|C29
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 398: Line 407:
 
|J1.59
 
|J1.59
 
|LVDS1_D2_N
 
|LVDS1_D2_N
−
|TBD
+
|CPU.LVDS1_D2_N
−
|TBD
+
|C28
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 408: Line 417:
 
|J1.61
 
|J1.61
 
|LVDS1_D2_P
 
|LVDS1_D2_P
−
|TBD
+
|CPU.LVDS1_D2_P
−
|TBD
+
|B29
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 418: Line 427:
 
|J1.63
 
|J1.63
 
|LVDS1_CLK_N
 
|LVDS1_CLK_N
−
|TBD
+
|CPU.LVDS1_CLK_N
−
|TBD
+
|B28
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 428: Line 437:
 
|J1.65
 
|J1.65
 
|LVDS1_CLK_P
 
|LVDS1_CLK_P
−
|TBD
+
|CPU.LVDS1_CLK_P
−
|TBD
+
|A28
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 438: Line 447:
 
|J1.67
 
|J1.67
 
|LVDS1_D1_N
 
|LVDS1_D1_N
−
|TBD
+
|CPU.LVDS1_D1_N
−
|TBD
+
|B27
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 448: Line 457:
 
|J1.69
 
|J1.69
 
|LVDS1_D1_P
 
|LVDS1_D1_P
−
|TBD
+
|CPU.LVDS1_D1_P
−
|TBD
+
|A27
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 458: Line 467:
 
|J1.71
 
|J1.71
 
|LVDS1_D0_N
 
|LVDS1_D0_N
−
|TBD
+
|CPU.LVDS1_D0_N
−
|TBD
+
|B26
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 468: Line 477:
 
|J1.73
 
|J1.73
 
|LVDS1_D0_P
 
|LVDS1_D0_P
−
|TBD
+
|CPU.LVDS1_D0_P
−
|TBD
+
|A26
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 488: Line 497:
 
|J1.77
 
|J1.77
 
|MIPI_CSI2_D0_P
 
|MIPI_CSI2_D0_P
−
|TBD
+
|CPU.MIPI_CSI2_D0_P
−
|TBD
+
|A25
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 498: Line 507:
 
|J1.79
 
|J1.79
 
|MIPI_CSI2_D0_N
 
|MIPI_CSI2_D0_N
−
|TBD
+
|CPU.MIPI_CSI2_D0_N
−
|TBD
+
|B25
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 508: Line 517:
 
|J1.81
 
|J1.81
 
|MIPI_CSI2_D1_P
 
|MIPI_CSI2_D1_P
−
|TBD
+
|CPU.MIPI_CSI2_D1_P
−
|TBD
+
|A24
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 518: Line 527:
 
|J1.83
 
|J1.83
 
|MIPI_CSI2_D1_N
 
|MIPI_CSI2_D1_N
−
|TBD
+
|CPU.MIPI_CSI2_D1_N
−
|TBD
+
|B24
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 528: Line 537:
 
|J1.85
 
|J1.85
 
|MIPI_CSI2_CLK_P
 
|MIPI_CSI2_CLK_P
−
|TBD
+
|CPU.MIPI_CSI2_CLK_P
−
|TBD
+
|A23
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 538: Line 547:
 
|J1.87
 
|J1.87
 
|MIPI_CSI2_CLK_N
 
|MIPI_CSI2_CLK_N
−
|TBD
+
|CPU.MIPI_CSI2_CLK_N
−
|TBD
+
|B23
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 548: Line 557:
 
|J1.89
 
|J1.89
 
|MIPI_CSI2_D2_P
 
|MIPI_CSI2_D2_P
−
|TBD
+
|CPU.MIPI_CSI2_D2_P
−
|TBD
+
|A22
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 558: Line 567:
 
|J1.91
 
|J1.91
 
|MIPI_CSI2_D2_N
 
|MIPI_CSI2_D2_N
−
|TBD
+
|CPU.MIPI_CSI2_D2_N
−
|TBD
+
|B22
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
−
|
+
|
 
|
 
|
 
|-
 
|-
 
|J1.93
 
|J1.93
 
|MIPI_CSI2_D3_P
 
|MIPI_CSI2_D3_P
−
|TBD
+
|CPU.MIPI_CSI2_D3_P
−
|TBD
+
|A21
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 578: Line 587:
 
|J1.95
 
|J1.95
 
|MIPI_CSI2_D3_N
 
|MIPI_CSI2_D3_N
−
|TBD
+
|CPU.MIPI_CSI2_D3_N
−
|TBD
+
|B21
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 598: Line 607:
 
|J1.99
 
|J1.99
 
|MIPI_CSI1_D3_P
 
|MIPI_CSI1_D3_P
−
|TBD
+
|CPU.MIPI_CSI1_D3_P
−
|TBD
+
|D26
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 608: Line 617:
 
|J1.101
 
|J1.101
 
|MIPI_CSI1_D3_N
 
|MIPI_CSI1_D3_N
−
|TBD
+
|CPU.MIPI_CSI1_D3_N
−
|TBD
+
|E26
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 618: Line 627:
 
|J1.103
 
|J1.103
 
|MIPI_CSI1_D2_P
 
|MIPI_CSI1_D2_P
−
|TBD
+
|CPU.MIPI_CSI1_D2_P
−
|TBD
+
|D24
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 628: Line 637:
 
|J1.105
 
|J1.105
 
|MIPI_CSI1_D2_N
 
|MIPI_CSI1_D2_N
−
|TBD
+
|CPU.MIPI_CSI1_D2_N
−
|TBD
+
|E24
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 638: Line 647:
 
|J1.107
 
|J1.107
 
|MIPI_CSI1_CLK_P
 
|MIPI_CSI1_CLK_P
−
|TBD
+
|CPU.MIPI_CSI1_CLK_P
−
|TBD
+
|D22
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 648: Line 657:
 
|J1.109
 
|J1.109
 
|MIPI_CSI1_CLK_N
 
|MIPI_CSI1_CLK_N
−
|TBD
+
|CPU.MIPI_CSI1_CLK_N
−
|TBD
+
|E22
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 658: Line 667:
 
|J1.111
 
|J1.111
 
|MIPI_CSI1_D1_P
 
|MIPI_CSI1_D1_P
−
|TBD
+
|CPU.MIPI_CSI1_D1_P
−
|TBD
+
|D20
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 668: Line 677:
 
|J1.113
 
|J1.113
 
|MIPI_CSI1_D1_N
 
|MIPI_CSI1_D1_N
−
|TBD
+
|CPU.MIPI_CSI1_D1_N
−
|TBD
+
|E20
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 678: Line 687:
 
|J1.115
 
|J1.115
 
|MIPI_CSI1_D0_P
 
|MIPI_CSI1_D0_P
−
|TBD
+
|CPU.MIPI_CSI1_D0_P
−
|TBD
+
|D18
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 688: Line 697:
 
|J1.117
 
|J1.117
 
|MIPI_CSI1_D0_N
 
|MIPI_CSI1_D0_N
−
|TBD
+
|CPU.MIPI_CSI1_D0_N
−
|TBD
+
|E18
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 708: Line 717:
 
|J1.121
 
|J1.121
 
|MIPI_DSI1_D3_P
 
|MIPI_DSI1_D3_P
−
|TBD
+
|CPU.MIPI_DSI1_D3_P
−
|TBD
+
|A20
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 718: Line 727:
 
|J1.123
 
|J1.123
 
|MIPI_DSI1_D3_N
 
|MIPI_DSI1_D3_N
−
|TBD
+
|CPU.MIPI_DSI1_D3_N
−
|TBD
+
|B20
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 728: Line 737:
 
|J1.125
 
|J1.125
 
|MIPI_DSI1_D2_P
 
|MIPI_DSI1_D2_P
−
|TBD
+
|CPU.MIPI_DSI1_D2_P
−
|TBD
+
|A19
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 738: Line 747:
 
|J1.127
 
|J1.127
 
|MIPI_DSI1_D2_N
 
|MIPI_DSI1_D2_N
−
|TBD
+
|CPU.MIPI_DSI1_D2_N
−
|TBD
+
|B19
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 748: Line 757:
 
|J1.129
 
|J1.129
 
|MIPI_DSI1_CLK_P
 
|MIPI_DSI1_CLK_P
−
|TBD
+
|CPU.MIPI_DSI1_CLK_P
−
|TBD
+
|A18
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 758: Line 767:
 
|J1.131
 
|J1.131
 
|MIPI_DSI1_CLK_N
 
|MIPI_DSI1_CLK_N
−
|TBD
+
|CPU.MIPI_DSI1_CLK_N
−
|TBD
+
|B18
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 768: Line 777:
 
|J1.133
 
|J1.133
 
|MIPI_DSI1_D1_P
 
|MIPI_DSI1_D1_P
−
|TBD
+
|CPU.MIPI_DSI1_D1_P
−
|TBD
+
|A17
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 778: Line 787:
 
|J1.135
 
|J1.135
 
|MIPI_DSI1_D1_N
 
|MIPI_DSI1_D1_N
−
|TBD
+
|CPU.MIPI_DSI1_D1_N
−
|TBD
+
|B17
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 788: Line 797:
 
|J1.137
 
|J1.137
 
|MIPI_DSI1_D0_P
 
|MIPI_DSI1_D0_P
−
|TBD
+
|CPU.MIPI_DSI1_D0_P
−
|TBD
+
|A16
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 798: Line 807:
 
|J1.139
 
|J1.139
 
|MIPI_DSI1_D0_N
 
|MIPI_DSI1_D0_N
−
|TBD
+
|CPU.MIPI_DSI1_D0_N
−
|TBD
+
|B16
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
−
|
+
|
 
|
 
|
 
|-
 
|-
Line 818: Line 827:
 
|J1.143
 
|J1.143
 
|JTAG_MOD
 
|JTAG_MOD
−
|TBD
+
|CPU.JTAG_MOD
−
|TBD
+
|G20
−
|TBD
+
|NVCC_3V3
−
|TBD
+
|I/O
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 828: Line 837:
 
|J1.145
 
|J1.145
 
|JTAG_TCK
 
|JTAG_TCK
−
|TBD
+
|CPU.JTAG_TCK
−
|TBD
+
|G18
−
|TBD
+
|NVCC_3V3
−
|TBD
+
|I/O
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 838: Line 847:
 
|J1.147
 
|J1.147
 
|JTAG_TDI
 
|JTAG_TDI
−
|TBD
+
|CPU.JTAG_TDI
−
|TBD
+
|G16
−
|TBD
+
|NVCC_3V3
−
|TBD
+
|I
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 848: Line 857:
 
|J1.149
 
|J1.149
 
|JTAG_TMS
 
|JTAG_TMS
−
|TBD
+
|CPU.JTAG_TMS
−
|TBD
+
|G14
−
|TBD
+
|NVCC_3V3
−
|TBD
+
|I/O
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 858: Line 867:
 
|J1.151
 
|J1.151
 
|JTAG_TDO
 
|JTAG_TDO
−
|TBD
+
|CPU.JTAG_TDO
−
|TBD
+
|F14
−
|TBD
+
|NVCC_3V3
−
|TBD
+
|O
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 878: Line 887:
 
|J1.155
 
|J1.155
 
|PCIE_REF_PAD_CLK_P
 
|PCIE_REF_PAD_CLK_P
−
|TBD
+
|CPU.PCIE_REF_PAD_CLK_P
−
|TBD
+
|D16
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
−
|
+
|
 
|
 
|
 
|-
 
|-
 
|J1.157
 
|J1.157
 
|PCIE_REF_PAD_CLK_N
 
|PCIE_REF_PAD_CLK_N
−
|TBD
+
|CPU.PCIE_REF_PAD_CLK_N
−
|TBD
+
|E16
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 898: Line 907:
 
|J1.159
 
|J1.159
 
|PCIE_TXN_P
 
|PCIE_TXN_P
−
|TBD
+
|CPU.PCIE_TXN_P
−
|TBD
+
|A15
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 908: Line 917:
 
|J1.161
 
|J1.161
 
|PCIE_TXN_N
 
|PCIE_TXN_N
−
|TBD
+
|CPU.PCIE_TXN_N
−
|TBD
+
|B15
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 918: Line 927:
 
|J1.163
 
|J1.163
 
|PCIE_RXN_P
 
|PCIE_RXN_P
−
|TBD
+
|CPU.PCIE_RXN_P
−
|TBD
+
|A14
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 928: Line 937:
 
|J1.165
 
|J1.165
 
|PCIE_RXN_N
 
|PCIE_RXN_N
−
|TBD
+
|CPU.PCIE_RXN_N
−
|TBD
+
|B14
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 948: Line 957:
 
|J1.169
 
|J1.169
 
|USB2_VBUS
 
|USB2_VBUS
−
|TBD
+
|USB2_VBUS
−
|TBD
+
| -
−
|TBD
+
| -
−
|TBD
+
|S
−
|TBD
+
|See USB section for details (5-20V tolerance)
 
|
 
|
 
|
 
|
Line 958: Line 967:
 
|J1.171
 
|J1.171
 
|USB2_ID
 
|USB2_ID
−
|TBD
+
|CPU.USB2_ID
−
|TBD
+
|E12
−
|TBD
+
|NVCC_3V3
−
|TBD
+
|I
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 968: Line 977:
 
|J1.173
 
|J1.173
 
|USB2_D_P
 
|USB2_D_P
−
|TBD
+
|CPU.USB2_D_P
−
|TBD
+
|D14
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 978: Line 987:
 
|J1.175
 
|J1.175
 
|USB2_D_N
 
|USB2_D_N
−
|TBD
+
|CPU.USB2_D_N
−
|TBD
+
|E14
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 998: Line 1,007:
 
|J1.179
 
|J1.179
 
|USB2_TX_P
 
|USB2_TX_P
−
|TBD
+
|CPU.USB2_TX_P
−
|TBD
+
|A13
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 1,008: Line 1,017:
 
|J1.181
 
|J1.181
 
|USB2_TX_N
 
|USB2_TX_N
−
|TBD
+
|CPU.USB2_TX_N
−
|TBD
+
|B13
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 1,018: Line 1,027:
 
|J1.183
 
|J1.183
 
|USB2_RX_P
 
|USB2_RX_P
−
|TBD
+
|CPU.USB2_RX_P
−
|TBD
+
|A12
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 1,028: Line 1,037:
 
|J1.185
 
|J1.185
 
|USB2_RX_N
 
|USB2_RX_N
−
|TBD
+
|CPU.USB2_RX_N
−
|TBD
+
|B12
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 1,048: Line 1,057:
 
|J1.189
 
|J1.189
 
|USB1_VBUS
 
|USB1_VBUS
−
|TBD
+
|USB1_VBUS
−
|TBD
+
| -
−
|TBD
+
| -
−
|TBD
+
|S
−
|TBD
+
|See USB section for details (5-20V tolerance)
 
|
 
|
 
|
 
|
Line 1,058: Line 1,067:
 
|J1.191
 
|J1.191
 
|USB1_ID
 
|USB1_ID
−
|TBD
+
|CPOU.USB1_ID
−
|TBD
+
|B11
−
|TBD
+
|NVCC_3V3
−
|TBD
+
|I
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 1,068: Line 1,077:
 
|J1.193
 
|J1.193
 
|USB1_D_P
 
|USB1_D_P
−
|TBD
+
|CPU.USB1_D_P
−
|TBD
+
|D10
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 1,078: Line 1,087:
 
|J1.195
 
|J1.195
 
|USB1_D_N
 
|USB1_D_N
−
|TBD
+
|CPU.USB1_D_N
−
|TBD
+
|E10
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 1,098: Line 1,107:
 
|J1.199
 
|J1.199
 
|USB1_TX_P
 
|USB1_TX_P
−
|TBD
+
|CPU.USB1_TX_P
−
|TBD
+
|A10
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 1,108: Line 1,117:
 
|J1.201
 
|J1.201
 
|USB1_TX_N
 
|USB1_TX_N
−
|TBD
+
|CPU.USB1_TX_N
−
|TBD
+
|B10
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 1,118: Line 1,127:
 
|J1.203
 
|J1.203
 
|USB1_RX_P
 
|USB1_RX_P
−
|TBD
+
|CPU.USB1_RX_P
−
|TBD
+
|A9
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 1,128: Line 1,137:
 
|J1.205
 
|J1.205
 
|USB1_RX_N
 
|USB1_RX_N
−
|TBD
+
|CPU.USB1_RX_N
−
|TBD
+
|B9
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 1,148: Line 1,157:
 
| rowspan="6" |J1.209
 
| rowspan="6" |J1.209
 
| rowspan="6" |GPIO1_IO08
 
| rowspan="6" |GPIO1_IO08
−
| rowspan="6" |TBD
+
| rowspan="6" |CPU.GPIO1_IO08
−
| rowspan="6" |TBD
+
| rowspan="6" |A8
−
| rowspan="6" |TBD
+
| rowspan="6" |NVCC_3V3
−
| rowspan="6" |TBD
+
| rowspan="6" |I/O
−
| rowspan="6" |TBD
+
| rowspan="6" |
−
|Pin ALT-0
+
|Pin ALT-0
−
|GPIO1_IO08
+
|GPIO1_IO08
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
Line 1,173: Line 1,182:
 
| rowspan="5" |J1.211
 
| rowspan="5" |J1.211
 
| rowspan="5" |GPIO1_IO11
 
| rowspan="5" |GPIO1_IO11
−
| rowspan="5" |TBD
+
| rowspan="5" |CPU.GPIO1_IO11
−
| rowspan="5" |TBD
+
| rowspan="5" |D8
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|GPIO1_IO11
 
|GPIO1_IO11
Line 1,195: Line 1,204:
 
| rowspan="6" |J1.213
 
| rowspan="6" |J1.213
 
| rowspan="6" |GPIO1_IO09
 
| rowspan="6" |GPIO1_IO09
−
| rowspan="6" |TBD
+
| rowspan="6" |CPU.GPIO1_IO09
−
| rowspan="6" |TBD
+
| rowspan="6" |B8
−
| rowspan="6" |TBD
+
| rowspan="6" |NVCC_3V3
−
| rowspan="6" |TBD
+
| rowspan="6" |I/O
−
| rowspan="6" |TBD
+
| rowspan="6" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|GPIO1_IO09
 
|GPIO1_IO09
Line 1,220: Line 1,229:
 
| rowspan="4" |J1.215
 
| rowspan="4" |J1.215
 
| rowspan="4" |GPIO1_IO00
 
| rowspan="4" |GPIO1_IO00
−
| rowspan="4" |TBD
+
| rowspan="4" |CPU.GPIO1_IO00
−
| rowspan="4" |TBD
+
| rowspan="4" |A7
−
| rowspan="4" |TBD
+
| rowspan="4" |NVCC_3V3
−
| rowspan="4" |TBD
+
| rowspan="4" |I/O
−
| rowspan="4" |TBD
+
| rowspan="4" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|GPIO1_IO00
 
|GPIO1_IO00
Line 1,239: Line 1,248:
 
| rowspan="4" |J1.217
 
| rowspan="4" |J1.217
 
| rowspan="4" |GPIO1_IO01
 
| rowspan="4" |GPIO1_IO01
−
| rowspan="4" |TBD
+
| rowspan="4" |CPU.GPIO1_IO01
−
| rowspan="4" |TBD
+
| rowspan="4" |E8
−
| rowspan="4" |TBD
+
| rowspan="4" |NVCC_3V3
−
| rowspan="4" |TBD
+
| rowspan="4" |I/O
−
| rowspan="4" |TBD
+
| rowspan="4" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|GPIO1_IO01
 
|GPIO1_IO01
Line 1,258: Line 1,267:
 
| rowspan="3" |J1.219
 
| rowspan="3" |J1.219
 
| rowspan="3" |GPIO1_IO10
 
| rowspan="3" |GPIO1_IO10
−
| rowspan="3" |TBD
+
| rowspan="3" |CPU.GPIO1_IO10
−
| rowspan="3" |TBD
+
| rowspan="3" |B7
−
| rowspan="3" |TBD
+
| rowspan="3" |NVCC_3V3
−
| rowspan="3" |TBD
+
| rowspan="3" |I/O
−
| rowspan="3" |TBD
+
| rowspan="3" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|GPIO1_IO10
 
|GPIO1_IO10
Line 1,274: Line 1,283:
 
| rowspan="3" |J1.221
 
| rowspan="3" |J1.221
 
| rowspan="3" |GPIO1_IO13
 
| rowspan="3" |GPIO1_IO13
−
| rowspan="3" |TBD
+
| rowspan="3" |CPU.GPIO1_IO13
−
| rowspan="3" |TBD
+
| rowspan="3" |A6
−
| rowspan="3" |TBD
+
| rowspan="3" |NVCC_3V3
−
| rowspan="3" |TBD
+
| rowspan="3" |I/O
−
| rowspan="3" |TBD
+
| rowspan="3" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|GPIO1_IO13
 
|GPIO1_IO13
Line 1,290: Line 1,299:
 
| rowspan="3" |J1.223
 
| rowspan="3" |J1.223
 
| rowspan="3" |GPIO1_IO12
 
| rowspan="3" |GPIO1_IO12
−
| rowspan="3" |TBD
+
| rowspan="3" |CPU.GPIO1_IO12
−
| rowspan="3" |TBD
+
| rowspan="3" |A5
−
| rowspan="3" |TBD
+
| rowspan="3" |NVCC_3V3
−
| rowspan="3" |TBD
+
| rowspan="3" |I/O
−
| rowspan="3" |TBD
+
| rowspan="3" |
−
|Pin ALT-0
+
|Pin ALT-0
−
|GPIO1_IO12
+
|GPIO1_IO12
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
Line 1,306: Line 1,315:
 
| rowspan="5" |J1.225
 
| rowspan="5" |J1.225
 
| rowspan="5" |GPIO1_IO07
 
| rowspan="5" |GPIO1_IO07
−
| rowspan="5" |TBD
+
| rowspan="5" |CPU.GPIO1_IO07
−
| rowspan="5" |TBD
+
| rowspan="5" |F6
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|GPIO1_IO07
 
|GPIO1_IO07
Line 1,328: Line 1,337:
 
| rowspan="5" |J1.227
 
| rowspan="5" |J1.227
 
| rowspan="5" |GPIO1_IO15
 
| rowspan="5" |GPIO1_IO15
−
| rowspan="5" |TBD
+
| rowspan="5" |CPU.GPIO1_IO15
−
| rowspan="5" |TBD
+
| rowspan="5" |B5
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|GPIO1_IO15
 
|GPIO1_IO15
Line 1,350: Line 1,359:
 
| rowspan="5" |J1.229
 
| rowspan="5" |J1.229
 
| rowspan="5" |GPIO1_IO14
 
| rowspan="5" |GPIO1_IO14
−
| rowspan="5" |TBD
+
| rowspan="5" |CPU.GPIO1_IO14
−
| rowspan="5" |TBD
+
| rowspan="5" |A4
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|GPIO1_IO14
 
|GPIO1_IO14
Line 1,372: Line 1,381:
 
| rowspan="4" |J1.231
 
| rowspan="4" |J1.231
 
| rowspan="4" |GPIO1_IO05
 
| rowspan="4" |GPIO1_IO05
−
| rowspan="4" |TBD
+
| rowspan="4" |CPU.GPIO1_IO05
−
| rowspan="4" |TBD
+
| rowspan="4" |B4
−
| rowspan="4" |TBD
+
| rowspan="4" |NVCC_3V3
−
| rowspan="4" |TBD
+
| rowspan="4" |I/O
−
| rowspan="4" |TBD
+
| rowspan="4" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|GPIO1_IO05
 
|GPIO1_IO05
Line 1,391: Line 1,400:
 
| rowspan="5" |J1.233
 
| rowspan="5" |J1.233
 
| rowspan="5" |GPIO1_IO06
 
| rowspan="5" |GPIO1_IO06
−
| rowspan="5" |TBD
+
| rowspan="5" |CPU.GPIO1_IO06
−
| rowspan="5" |TBD
+
| rowspan="5" |A3
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|GPIO1_IO06
 
|GPIO1_IO06
Line 1,423: Line 1,432:
 
|J1.237
 
|J1.237
 
|ETH0_TXRX3_M
 
|ETH0_TXRX3_M
−
|TBD
+
|LAN.TXTRM_D
−
|TBD
+
|11
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 1,433: Line 1,442:
 
|J1.239
 
|J1.239
 
|ETH0_TXRX3_P
 
|ETH0_TXRX3_P
−
|TBD
+
|LAN.TXTRP_D
−
|TBD
+
|10
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 1,443: Line 1,452:
 
|J1.241
 
|J1.241
 
|ETH0_TXRX2_M
 
|ETH0_TXRX2_M
−
|TBD
+
|LAN.TXTRM_C
−
|TBD
+
|8
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 1,453: Line 1,462:
 
|J1.243
 
|J1.243
 
|ETH0_TXRX2_P
 
|ETH0_TXRX2_P
−
|TBD
+
|LAN.TXTRP_C
−
|TBD
+
|7
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 1,463: Line 1,472:
 
|J1.245
 
|J1.245
 
|ETH0_TXRX1_M
 
|ETH0_TXRX1_M
−
|TBD
+
|LAN.TXTRM_B
−
|TBD
+
|6
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 1,473: Line 1,482:
 
|J1.247
 
|J1.247
 
|ETH0_TXRX1_P
 
|ETH0_TXRX1_P
−
|TBD
+
|LAN.TXTRP_B
−
|TBD
+
|5
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 1,483: Line 1,492:
 
|J1.249
 
|J1.249
 
|ETH0_TXRX0_M
 
|ETH0_TXRX0_M
−
|TBD
+
|LAN.TXTRM_A
−
|TBD
+
|3
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
−
|
+
|
 
|
 
|
 
|-
 
|-
 
|J1.251
 
|J1.251
 
|ETH0_TXRX0_P
 
|ETH0_TXRX0_P
−
|TBD
+
|LAN.TXTRP_A
−
|TBD
+
|2
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
 
|
 
|
 
|
 
|
Line 1,513: Line 1,522:
 
|J1.255
 
|J1.255
 
|ETH0_LED1
 
|ETH0_LED1
−
|TBD
+
|LAN.LED2
−
|TBD
+
|15
−
|TBD
+
|VDD_1V8
−
|TBD
+
|O
−
|TBD
+
|Must be level translated if used @ 3V3
 +
Internally pulled-up to 1.8V during bootstrap
 
|
 
|
 
|
 
|
Line 1,523: Line 1,533:
 
|J1.257
 
|J1.257
 
|ETH0_LED2
 
|ETH0_LED2
−
|TBD
+
|LAN.LED1/PME_N1
−
|TBD
+
|17
−
|TBD
+
|VDD_1V8
−
|TBD
+
|O
−
|TBD
+
|Must be level translated if used @ 3V3
 +
Internally pulled-up to 1.8V during bootstrap
 
|
 
|
 
|
 
|
Line 1,627: Line 1,638:
 
| rowspan="5" |J1.16
 
| rowspan="5" |J1.16
 
| rowspan="5" |SD1_CLK
 
| rowspan="5" |SD1_CLK
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_SD1
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|USDHC1_CLK
 
|USDHC1_CLK
Line 1,649: Line 1,660:
 
| rowspan="5" |J1.18
 
| rowspan="5" |J1.18
 
| rowspan="5" |SD1_CMD
 
| rowspan="5" |SD1_CMD
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_SD1
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|USDHC1_CMD
 
|USDHC1_CMD
Line 1,671: Line 1,682:
 
| rowspan="5" |J1.20
 
| rowspan="5" |J1.20
 
| rowspan="5" |SD1_DATA0
 
| rowspan="5" |SD1_DATA0
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_SD1
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|USDHC1_DATA0
 
|USDHC1_DATA0
Line 1,693: Line 1,704:
 
| rowspan="5" |J1.22
 
| rowspan="5" |J1.22
 
| rowspan="5" |SD1_DATA1
 
| rowspan="5" |SD1_DATA1
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_SD1
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|USDHC1_DATA1
 
|USDHC1_DATA1
Line 1,715: Line 1,726:
 
| rowspan="5" |J1.24
 
| rowspan="5" |J1.24
 
| rowspan="5" |SD1_DATA2
 
| rowspan="5" |SD1_DATA2
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_SD1
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
+
|Pin ALT-0
−
|Pin ALT-0
 
 
|USDHC1_DATA2
 
|USDHC1_DATA2
 
|-
 
|-
Line 1,737: Line 1,748:
 
| rowspan="5" |J1.26
 
| rowspan="5" |J1.26
 
| rowspan="5" |SD1_DATA3
 
| rowspan="5" |SD1_DATA3
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_SD1
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|USDHC1_DATA3
 
|USDHC1_DATA3
Line 1,759: Line 1,770:
 
| rowspan="5" |J1.28
 
| rowspan="5" |J1.28
 
| rowspan="5" |SD1_DATA4
 
| rowspan="5" |SD1_DATA4
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_SD1
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|USDHC1_DATA4
 
|USDHC1_DATA4
Line 1,781: Line 1,792:
 
| rowspan="5" |J1.30
 
| rowspan="5" |J1.30
 
| rowspan="5" |SD1_DATA5
 
| rowspan="5" |SD1_DATA5
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_SD1
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|USDHC1_DATA5
 
|USDHC1_DATA5
Line 1,803: Line 1,814:
 
| rowspan="6" |J1.32
 
| rowspan="6" |J1.32
 
| rowspan="6" |SD1_DATA6
 
| rowspan="6" |SD1_DATA6
 +
| rowspan="6" |CPU.
 
| rowspan="6" |TBD
 
| rowspan="6" |TBD
−
| rowspan="6" |TBD
+
| rowspan="6" |NVCC_SD1
−
| rowspan="6" |TBD
+
| rowspan="6" |I/O
−
| rowspan="6" |TBD
+
| rowspan="6" |
−
| rowspan="6" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|USDHC1_DATA6
 
|USDHC1_DATA6
Line 1,828: Line 1,839:
 
| rowspan="5" |J1.34
 
| rowspan="5" |J1.34
 
| rowspan="5" |SD1_DATA7
 
| rowspan="5" |SD1_DATA7
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_SD1
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|USDHC1_DATA7
 
|USDHC1_DATA7
Line 1,850: Line 1,861:
 
| rowspan="5" |J1.36
 
| rowspan="5" |J1.36
 
| rowspan="5" |SD1_RESET_B
 
| rowspan="5" |SD1_RESET_B
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_SD1
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|USDHC1_RESET_B
 
|USDHC1_RESET_B
Line 1,872: Line 1,883:
 
| rowspan="4" |J1.38
 
| rowspan="4" |J1.38
 
| rowspan="4" |SD1_STROBE
 
| rowspan="4" |SD1_STROBE
 +
| rowspan="4" |CPU.
 
| rowspan="4" |TBD
 
| rowspan="4" |TBD
−
| rowspan="4" |TBD
+
| rowspan="4" |NVCC_SD1
−
| rowspan="4" |TBD
+
| rowspan="4" |I/O
−
| rowspan="4" |TBD
+
| rowspan="4" |
−
| rowspan="4" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|USDHC1_STROBE
 
|USDHC1_STROBE
Line 1,901: Line 1,912:
 
| rowspan="2" |J1.42
 
| rowspan="2" |J1.42
 
| rowspan="2" |SD2_CD_B
 
| rowspan="2" |SD2_CD_B
 +
| rowspan="2" |CPU.
 
| rowspan="2" |TBD
 
| rowspan="2" |TBD
−
| rowspan="2" |TBD
+
| rowspan="2" |NVCC_SD2
−
| rowspan="2" |TBD
+
| rowspan="2" |I/O
−
| rowspan="2" |TBD
+
| rowspan="2" |
−
| rowspan="2" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|USDHC2_CD_B
 
|USDHC2_CD_B
Line 1,914: Line 1,925:
 
| rowspan="4" |J1.44
 
| rowspan="4" |J1.44
 
| rowspan="4" |SD2_CLK
 
| rowspan="4" |SD2_CLK
 +
| rowspan="4" |CPU.
 
| rowspan="4" |TBD
 
| rowspan="4" |TBD
−
| rowspan="4" |TBD
+
| rowspan="4" |NVCC_SD2
−
| rowspan="4" |TBD
+
| rowspan="4" |I/O
−
| rowspan="4" |TBD
+
| rowspan="4" |
−
| rowspan="4" |TBD
+
|Pin ALT-0
−
|Pin ALT-0
+
|USDHC2_CLK
−
|USDHC2_CLK
 
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
Line 1,933: Line 1,944:
 
| rowspan="5" |J1.46
 
| rowspan="5" |J1.46
 
| rowspan="5" |SD2_CMD
 
| rowspan="5" |SD2_CMD
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_SD2
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|USDHC2_CMD
 
|USDHC2_CMD
Line 1,955: Line 1,966:
 
| rowspan="5" |J1.48
 
| rowspan="5" |J1.48
 
| rowspan="5" |SD2_DATA0
 
| rowspan="5" |SD2_DATA0
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_SD2
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|USDHC2_DATA0
 
|USDHC2_DATA0
Line 1,977: Line 1,988:
 
| rowspan="5" |J1.50
 
| rowspan="5" |J1.50
 
| rowspan="5" |SD2_DATA1
 
| rowspan="5" |SD2_DATA1
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_SD2
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|USDHC2_DATA1
 
|USDHC2_DATA1
Line 1,999: Line 2,010:
 
| rowspan="5" |J1.52
 
| rowspan="5" |J1.52
 
| rowspan="5" |SD2_DATA2
 
| rowspan="5" |SD2_DATA2
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_SD2
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|USDHC2_DATA2
 
|USDHC2_DATA2
Line 2,021: Line 2,032:
 
| rowspan="6" |J1.54
 
| rowspan="6" |J1.54
 
| rowspan="6" |SD2_DATA3
 
| rowspan="6" |SD2_DATA3
 +
| rowspan="6" |CPU.
 
| rowspan="6" |TBD
 
| rowspan="6" |TBD
−
| rowspan="6" |TBD
+
| rowspan="6" |NVCC_SD2
−
| rowspan="6" |TBD
+
| rowspan="6" |I/O
−
| rowspan="6" |TBD
+
| rowspan="6" |
−
| rowspan="6" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|USDHC2_DATA3
 
|USDHC2_DATA3
Line 2,046: Line 2,057:
 
| rowspan="3" |J1.56
 
| rowspan="3" |J1.56
 
| rowspan="3" |SD2_RESET_B
 
| rowspan="3" |SD2_RESET_B
 +
| rowspan="3" |CPU.
 
| rowspan="3" |TBD
 
| rowspan="3" |TBD
−
| rowspan="3" |TBD
+
| rowspan="3" |NVCC_SD2
−
| rowspan="3" |TBD
+
| rowspan="3" |I/O
−
| rowspan="3" |TBD
+
| rowspan="3" |
−
| rowspan="3" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|USDHC2_RESET_B
 
|USDHC2_RESET_B
Line 2,062: Line 2,073:
 
| rowspan="3" |J1.58
 
| rowspan="3" |J1.58
 
| rowspan="3" |SD2_WP
 
| rowspan="3" |SD2_WP
 +
| rowspan="3" |CPU.
 
| rowspan="3" |TBD
 
| rowspan="3" |TBD
−
| rowspan="3" |TBD
+
| rowspan="3" |NVCC_SD2
−
| rowspan="3" |TBD
+
| rowspan="3" |I/O
−
| rowspan="3" |TBD
+
| rowspan="3" |
−
| rowspan="3" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|USDHC2_WP
 
|USDHC2_WP
Line 2,075: Line 2,086:
 
|Pin ALT-6
 
|Pin ALT-6
 
|CORESIGHT_EVENTI
 
|CORESIGHT_EVENTI
 +
|-
 +
|J1.58
 +
(both NAND and
 +
 +
NOR on board)
 +
|SD2_WP
 +
|CPU.
 +
|TBD
 +
|NVCC_SD2
 +
|O
 +
|internal use for
 +
NAND/NOR selection,
 +
 +
do not connect
 +
|
 +
|
 
|-
 
|-
 
|J1.60
 
|J1.60
Line 2,088: Line 2,115:
 
|J1.62
 
|J1.62
 
|CLKIN1
 
|CLKIN1
 +
|CPU.
 
|TBD
 
|TBD
−
|TBD
+
|NVCC_3V3
−
|TBD
+
|I
−
|TBD
+
|
−
|TBD
 
 
|
 
|
 
|
 
|
Line 2,098: Line 2,125:
 
|J1.64
 
|J1.64
 
|CLKIN2
 
|CLKIN2
 +
|CPU.
 
|TBD
 
|TBD
−
|TBD
+
|NVCC_3V3
−
|TBD
+
|I
−
|TBD
+
|
−
|TBD
 
 
|
 
|
 
|
 
|
Line 2,118: Line 2,145:
 
|J1.68
 
|J1.68
 
|CLKOUT1
 
|CLKOUT1
 +
|CPU.
 
|TBD
 
|TBD
−
|TBD
+
|NVCC_3V3
−
|TBD
+
|O
−
|TBD
+
|
−
|TBD
 
 
|
 
|
 
|
 
|
Line 2,128: Line 2,155:
 
|J1.70
 
|J1.70
 
|CLKOUT2
 
|CLKOUT2
 +
|CPU.
 
|TBD
 
|TBD
−
|TBD
+
|NVCC_3V3
−
|TBD
+
|O
−
|TBD
+
|
−
|TBD
 
 
|
 
|
 
|
 
|
Line 2,148: Line 2,175:
 
| rowspan="4" |J1.74
 
| rowspan="4" |J1.74
 
| rowspan="4" |HDMI_CEC
 
| rowspan="4" |HDMI_CEC
 +
| rowspan="4" |CPU.
 
| rowspan="4" |TBD
 
| rowspan="4" |TBD
−
| rowspan="4" |TBD
+
| rowspan="4" |NVCC_3V3
−
| rowspan="4" |TBD
+
| rowspan="4" |I/O
−
| rowspan="4" |TBD
+
| rowspan="4" |
−
| rowspan="4" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|HDMIMIX_EARC_CEC
 
|HDMIMIX_EARC_CEC
Line 2,167: Line 2,194:
 
| rowspan="4" |J1.76
 
| rowspan="4" |J1.76
 
| rowspan="4" |HDMI_DDC_SCL
 
| rowspan="4" |HDMI_DDC_SCL
 +
| rowspan="4" |CPU.
 
| rowspan="4" |TBD
 
| rowspan="4" |TBD
−
| rowspan="4" |TBD
+
| rowspan="4" |NVCC_3V3
−
| rowspan="4" |TBD
+
| rowspan="4" |I/O
−
| rowspan="4" |TBD
+
| rowspan="4" |
−
| rowspan="4" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|HDMIMIX_EARC_SCL
 
|HDMIMIX_EARC_SCL
Line 2,186: Line 2,213:
 
| rowspan="4" |J1.78
 
| rowspan="4" |J1.78
 
| rowspan="4" |HDMI_DDC_SDA
 
| rowspan="4" |HDMI_DDC_SDA
 +
| rowspan="4" |CPU.
 
| rowspan="4" |TBD
 
| rowspan="4" |TBD
−
| rowspan="4" |TBD
+
| rowspan="4" |NVCC_3V3
−
| rowspan="4" |TBD
+
| rowspan="4" |I/O
−
| rowspan="4" |TBD
+
| rowspan="4" |
−
| rowspan="4" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|HDMIMIX_EARC_SDA
 
|HDMIMIX_EARC_SDA
Line 2,205: Line 2,232:
 
| rowspan="5" |J1.80
 
| rowspan="5" |J1.80
 
| rowspan="5" |HDMI_HPD
 
| rowspan="5" |HDMI_HPD
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|HDMIMIX_EARC_DC_HPD
 
|HDMIMIX_EARC_DC_HPD
Line 2,237: Line 2,264:
 
|J1.84
 
|J1.84
 
|HDMI_TXC_N
 
|HDMI_TXC_N
 +
|CPU.
 
|TBD
 
|TBD
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
−
|TBD
 
 
|
 
|
 
|
 
|
Line 2,247: Line 2,274:
 
|J1.86
 
|J1.86
 
|HDMI_TXC_P
 
|HDMI_TXC_P
 +
|CPU.
 
|TBD
 
|TBD
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
−
|TBD
 
 
|
 
|
 
|
 
|
Line 2,257: Line 2,284:
 
|J1.88
 
|J1.88
 
|HDMI_TX0_N
 
|HDMI_TX0_N
 +
|CPU.
 
|TBD
 
|TBD
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
−
|TBD
 
 
|
 
|
 
|
 
|
Line 2,267: Line 2,294:
 
|J1.90
 
|J1.90
 
|HDMI_TX0_P
 
|HDMI_TX0_P
 +
|CPU.
 
|TBD
 
|TBD
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
−
|TBD
 
 
|
 
|
 
|
 
|
Line 2,277: Line 2,304:
 
|J1.92
 
|J1.92
 
|HDMI_TX1_N
 
|HDMI_TX1_N
 +
|CPU.
 
|TBD
 
|TBD
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
−
|TBD
 
 
|
 
|
 
|
 
|
Line 2,287: Line 2,314:
 
|J1.94
 
|J1.94
 
|HDMI_TX1_P
 
|HDMI_TX1_P
 +
|CPU.
 
|TBD
 
|TBD
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
−
|TBD
 
 
|
 
|
 
|
 
|
Line 2,297: Line 2,324:
 
|J1.96
 
|J1.96
 
|HDMI_TX2_N
 
|HDMI_TX2_N
 +
|CPU.
 
|TBD
 
|TBD
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
−
|TBD
 
 
|
 
|
 
|
 
|
Line 2,307: Line 2,334:
 
|J1.98
 
|J1.98
 
|HDMI_TX2_P
 
|HDMI_TX2_P
 +
|CPU.
 
|TBD
 
|TBD
−
|TBD
+
| -
−
|TBD
+
|D
−
|TBD
+
|
−
|TBD
 
 
|
 
|
 
|
 
|
Line 2,327: Line 2,354:
 
|J1.102
 
|J1.102
 
|EARC_P_UTIL
 
|EARC_P_UTIL
 +
|CPU.
 
|TBD
 
|TBD
−
|TBD
+
|VDDA_1V8
−
|TBD
+
|D
−
|TBD
+
|
−
|TBD
 
 
|
 
|
 
|
 
|
Line 2,337: Line 2,364:
 
|J1.104
 
|J1.104
 
|EARC_N_HPD
 
|EARC_N_HPD
 +
|CPU.
 
|TBD
 
|TBD
−
|TBD
+
|VDDA_1V8
−
|TBD
+
|D
−
|TBD
+
|
−
|TBD
 
 
|
 
|
 
|
 
|
Line 2,347: Line 2,374:
 
|J1.106
 
|J1.106
 
|EARC_AUX
 
|EARC_AUX
 +
|CPU.
 
|TBD
 
|TBD
−
|TBD
+
|VDDA_1V8
−
|TBD
+
|I/O
−
|TBD
+
|
−
|TBD
 
 
|
 
|
 
|
 
|
Line 2,367: Line 2,394:
 
| rowspan="5" |J1.110
 
| rowspan="5" |J1.110
 
| rowspan="5" |ECSPI1_MISO
 
| rowspan="5" |ECSPI1_MISO
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|ECSPI1_MISO
 
|ECSPI1_MISO
Line 2,389: Line 2,416:
 
| rowspan="5" |J1.112
 
| rowspan="5" |J1.112
 
| rowspan="5" |ECSPI1_MOSI
 
| rowspan="5" |ECSPI1_MOSI
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|ECSPI1_MOSI
 
|ECSPI1_MOSI
Line 2,411: Line 2,438:
 
| rowspan="5" |J1.114
 
| rowspan="5" |J1.114
 
| rowspan="5" |ECSPI1_SCLK
 
| rowspan="5" |ECSPI1_SCLK
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|ECSPI1_SCLK
 
|ECSPI1_SCLK
Line 2,433: Line 2,460:
 
| rowspan="5" |J1.116
 
| rowspan="5" |J1.116
 
| rowspan="5" |ECSPI1_SS0
 
| rowspan="5" |ECSPI1_SS0
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|ECSPI1_SS0
 
|ECSPI1_SS0
Line 2,465: Line 2,492:
 
| rowspan="6" |J1.120
 
| rowspan="6" |J1.120
 
| rowspan="6" |ECSPI2_MISO
 
| rowspan="6" |ECSPI2_MISO
 +
| rowspan="6" |CPU.
 
| rowspan="6" |TBD
 
| rowspan="6" |TBD
−
| rowspan="6" |TBD
+
| rowspan="6" |NVCC_3V3
−
| rowspan="6" |TBD
+
| rowspan="6" |I/O
−
| rowspan="6" |TBD
+
| rowspan="6" |
−
| rowspan="6" |TBD
+
|Pin ALT-0
−
|Pin ALT-0
 
 
|ECSPI2_MISO
 
|ECSPI2_MISO
 
|-
 
|-
Line 2,490: Line 2,517:
 
| rowspan="5" |J1.122
 
| rowspan="5" |J1.122
 
| rowspan="5" |ECSPI2_MOSI
 
| rowspan="5" |ECSPI2_MOSI
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|ECSPI2_MOSI
 
|ECSPI2_MOSI
Line 2,512: Line 2,539:
 
| rowspan="5" |J1.124
 
| rowspan="5" |J1.124
 
| rowspan="5" |ECSPI2_SCLK
 
| rowspan="5" |ECSPI2_SCLK
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|ECSPI2_SCLK
 
|ECSPI2_SCLK
Line 2,534: Line 2,561:
 
| rowspan="5" |J1.126
 
| rowspan="5" |J1.126
 
| rowspan="5" |ECSPI2_SS0
 
| rowspan="5" |ECSPI2_SS0
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|ECSPI2_SS0
 
|ECSPI2_SS0
Line 2,567: Line 2,594:
 
| rowspan="4" |SPDIF_EXT_CLK//
 
| rowspan="4" |SPDIF_EXT_CLK//
 
ISP_FL_TRIG_0
 
ISP_FL_TRIG_0
 +
| rowspan="4" |CPU.
 
| rowspan="4" |TBD
 
| rowspan="4" |TBD
−
| rowspan="4" |TBD
+
| rowspan="4" |NVCC_3V3
−
| rowspan="4" |TBD
+
| rowspan="4" |I/O
−
| rowspan="4" |TBD
+
| rowspan="4" |
−
| rowspan="4" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SPDIF_EXT_CLK
 
|AUDIOMIX_SPDIF_EXT_CLK
Line 2,587: Line 2,614:
 
| rowspan="6" |SPDIF_RX//
 
| rowspan="6" |SPDIF_RX//
 
ISP_SHUTTER_TRIG_0
 
ISP_SHUTTER_TRIG_0
 +
| rowspan="6" |CPU.
 
| rowspan="6" |TBD
 
| rowspan="6" |TBD
−
| rowspan="6" |TBD
+
| rowspan="6" |NVCC_3V3
−
| rowspan="6" |TBD
+
| rowspan="6" |I/O
−
| rowspan="6" |TBD
+
| rowspan="6" |
−
| rowspan="6" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SPDIF_IN
 
|AUDIOMIX_SPDIF_IN
Line 2,613: Line 2,640:
 
| rowspan="6" |SPDIF_TX//
 
| rowspan="6" |SPDIF_TX//
 
ISP_FLASH_TRIG_0
 
ISP_FLASH_TRIG_0
 +
| rowspan="6" |CPU.
 
| rowspan="6" |TBD
 
| rowspan="6" |TBD
−
| rowspan="6" |TBD
+
| rowspan="6" |NVCC_3V3
−
| rowspan="6" |TBD
+
| rowspan="6" |I/O
−
| rowspan="6" |TBD
+
| rowspan="6" |
−
| rowspan="6" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SPDIF_OUT
 
|AUDIOMIX_SPDIF_OUT
Line 2,648: Line 2,675:
 
| rowspan="7" |J1.138
 
| rowspan="7" |J1.138
 
| rowspan="7" |SAI2_MCLK
 
| rowspan="7" |SAI2_MCLK
 +
| rowspan="7" |CPU.
 
| rowspan="7" |TBD
 
| rowspan="7" |TBD
−
| rowspan="7" |TBD
+
| rowspan="7" |NVCC_3V3
−
| rowspan="7" |TBD
+
| rowspan="7" |I/O
−
| rowspan="7" |TBD
+
| rowspan="7" |
−
| rowspan="7" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI2_MCLK
 
|AUDIOMIX_SAI2_MCLK
Line 2,676: Line 2,703:
 
| rowspan="6" |J1.140
 
| rowspan="6" |J1.140
 
| rowspan="6" |SAI2_RXC
 
| rowspan="6" |SAI2_RXC
 +
| rowspan="6" |CPU.
 
| rowspan="6" |TBD
 
| rowspan="6" |TBD
−
| rowspan="6" |TBD
+
| rowspan="6" |NVCC_3V3
−
| rowspan="6" |TBD
+
| rowspan="6" |I/O
−
| rowspan="6" |TBD
+
| rowspan="6" |
−
| rowspan="6" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI2_RX_BCLK
 
|AUDIOMIX_SAI2_RX_BCLK
Line 2,701: Line 2,728:
 
| rowspan="7" |J1.142
 
| rowspan="7" |J1.142
 
| rowspan="7" |SAI2_RXD0
 
| rowspan="7" |SAI2_RXD0
 +
| rowspan="7" |CPU.
 
| rowspan="7" |TBD
 
| rowspan="7" |TBD
−
| rowspan="7" |TBD
+
| rowspan="7" |NVCC_3V3
−
| rowspan="7" |TBD
+
| rowspan="7" |I/O
−
| rowspan="7" |TBD
+
| rowspan="7" |
−
| rowspan="7" |TBD
+
|Pin ALT-0
−
|Pin ALT-0
+
|AUDIOMIX_SAI2_RX_DATA[0]
−
|AUDIOMIX_SAI2_RX_DATA[0]
 
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
Line 2,729: Line 2,756:
 
| rowspan="7" |J1.144
 
| rowspan="7" |J1.144
 
| rowspan="7" |SAI2_RXFS
 
| rowspan="7" |SAI2_RXFS
 +
| rowspan="7" |CPU.
 
| rowspan="7" |TBD
 
| rowspan="7" |TBD
−
| rowspan="7" |TBD
+
| rowspan="7" |NVCC_3V3
−
| rowspan="7" |TBD
+
| rowspan="7" |I/O
−
| rowspan="7" |TBD
+
| rowspan="7" |
−
| rowspan="7" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI2_RX_SYNC
 
|AUDIOMIX_SAI2_RX_SYNC
Line 2,757: Line 2,784:
 
| rowspan="5" |J1.146
 
| rowspan="5" |J1.146
 
| rowspan="5" |SAI2_TXC
 
| rowspan="5" |SAI2_TXC
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI2_TX_BCLK
 
|AUDIOMIX_SAI2_TX_BCLK
Line 2,779: Line 2,806:
 
| rowspan="6" |J1.148
 
| rowspan="6" |J1.148
 
| rowspan="6" |SAI2_TXD0
 
| rowspan="6" |SAI2_TXD0
 +
| rowspan="6" |CPU.
 
| rowspan="6" |TBD
 
| rowspan="6" |TBD
−
| rowspan="6" |TBD
+
| rowspan="6" |NVCC_3V3
−
| rowspan="6" |TBD
+
| rowspan="6" |I/O
−
| rowspan="6" |TBD
+
| rowspan="6" |
−
| rowspan="6" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI2_TX_DATA[0]
 
|AUDIOMIX_SAI2_TX_DATA[0]
Line 2,804: Line 2,831:
 
| rowspan="7" |J1.150
 
| rowspan="7" |J1.150
 
| rowspan="7" |SAI2_TXFS
 
| rowspan="7" |SAI2_TXFS
 +
| rowspan="7" |CPU.
 
| rowspan="7" |TBD
 
| rowspan="7" |TBD
−
| rowspan="7" |TBD
+
| rowspan="7" |NVCC_3V3
−
| rowspan="7" |TBD
+
| rowspan="7" |I/O
−
| rowspan="7" |TBD
+
| rowspan="7" |
−
| rowspan="7" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI2_TX_SYNC
 
|AUDIOMIX_SAI2_TX_SYNC
Line 2,833: Line 2,860:
 
| rowspan="6" |SAI3_MCLK//
 
| rowspan="6" |SAI3_MCLK//
 
ISP_PRELIGHT_TRIG_0
 
ISP_PRELIGHT_TRIG_0
 +
| rowspan="6" |CPU.
 
| rowspan="6" |TBD
 
| rowspan="6" |TBD
−
| rowspan="6" |TBD
+
| rowspan="6" |NVCC_3V3
−
| rowspan="6" |TBD
+
| rowspan="6" |I/O
−
| rowspan="6" |TBD
+
| rowspan="6" |
−
| rowspan="6" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI3_MCLK
 
|AUDIOMIX_SAI3_MCLK
Line 2,859: Line 2,886:
 
| rowspan="7" |SAI3_RXC//
 
| rowspan="7" |SAI3_RXC//
 
ISP_SHUTTER_OPEN_0
 
ISP_SHUTTER_OPEN_0
 +
| rowspan="7" |CPU.
 
| rowspan="7" |TBD
 
| rowspan="7" |TBD
−
| rowspan="7" |TBD
+
| rowspan="7" |NVCC_3V3
−
| rowspan="7" |TBD
+
| rowspan="7" |I/O
−
| rowspan="7" |TBD
+
| rowspan="7" |
−
| rowspan="7" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI3_RX_BCLK
 
|AUDIOMIX_SAI3_RX_BCLK
Line 2,888: Line 2,915:
 
| rowspan="6" |SAI3_RXD//
 
| rowspan="6" |SAI3_RXD//
 
ISP_FL_TRIG_1
 
ISP_FL_TRIG_1
 +
| rowspan="6" |CPU.
 
| rowspan="6" |TBD
 
| rowspan="6" |TBD
−
| rowspan="6" |TBD
+
| rowspan="6" |NVCC_3V3
−
| rowspan="6" |TBD
+
| rowspan="6" |I/O
−
| rowspan="6" |TBD
+
| rowspan="6" |
−
| rowspan="6" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI3_RX_DATA[0]
 
|AUDIOMIX_SAI3_RX_DATA[0]
Line 2,914: Line 2,941:
 
| rowspan="7" |SAI3_RXFS//
 
| rowspan="7" |SAI3_RXFS//
 
ISP_SHUTTER_TRIG_1
 
ISP_SHUTTER_TRIG_1
 +
| rowspan="7" |CPU.
 
| rowspan="7" |TBD
 
| rowspan="7" |TBD
−
| rowspan="7" |TBD
+
| rowspan="7" |NVCC_3V3
−
| rowspan="7" |TBD
+
| rowspan="7" |I/O
−
| rowspan="7" |TBD
+
| rowspan="7" |
−
| rowspan="7" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI3_RX_SYNC
 
|AUDIOMIX_SAI3_RX_SYNC
Line 2,943: Line 2,970:
 
| rowspan="7" |SAI3_TXC//
 
| rowspan="7" |SAI3_TXC//
 
ISP_FLASH_TRIG_1
 
ISP_FLASH_TRIG_1
 +
| rowspan="7" |CPU.
 
| rowspan="7" |TBD
 
| rowspan="7" |TBD
−
| rowspan="7" |TBD
+
| rowspan="7" |NVCC_3V3
−
| rowspan="7" |TBD
+
| rowspan="7" |I/O
−
| rowspan="7" |TBD
+
| rowspan="7" |
−
| rowspan="7" |TBD
+
|Pin ALT-0
−
|Pin ALT-0
 
 
|AUDIOMIX_SAI3_TX_BCLK
 
|AUDIOMIX_SAI3_TX_BCLK
 
|-
 
|-
Line 2,972: Line 2,999:
 
| rowspan="7" |SAI3_TXD//
 
| rowspan="7" |SAI3_TXD//
 
ISP_PRELIGHT_TRIG_1
 
ISP_PRELIGHT_TRIG_1
 +
| rowspan="7" |CPU.
 
| rowspan="7" |TBD
 
| rowspan="7" |TBD
−
| rowspan="7" |TBD
+
| rowspan="7" |NVCC_3V3
−
| rowspan="7" |TBD
+
| rowspan="7" |I/O
−
| rowspan="7" |TBD
+
| rowspan="7" |
−
| rowspan="7" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI3_TX_DATA[0]
 
|AUDIOMIX_SAI3_TX_DATA[0]
Line 3,001: Line 3,028:
 
| rowspan="7" |SAI3_TXFS//
 
| rowspan="7" |SAI3_TXFS//
 
ISP_SHUTTER_OPEN_1
 
ISP_SHUTTER_OPEN_1
 +
| rowspan="7" |CPU.
 
| rowspan="7" |TBD
 
| rowspan="7" |TBD
−
| rowspan="7" |TBD
+
| rowspan="7" |NVCC_3V3
−
| rowspan="7" |TBD
+
| rowspan="7" |I/O
−
| rowspan="7" |TBD
+
| rowspan="7" |
−
| rowspan="7" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI3_TX_SYNC
 
|AUDIOMIX_SAI3_TX_SYNC
Line 3,029: Line 3,056:
 
| rowspan="6" |J1.166
 
| rowspan="6" |J1.166
 
| rowspan="6" |SAI5_MCLK
 
| rowspan="6" |SAI5_MCLK
 +
| rowspan="6" |CPU.
 
| rowspan="6" |TBD
 
| rowspan="6" |TBD
−
| rowspan="6" |TBD
+
| rowspan="6" |NVCC_3V3
−
| rowspan="6" |TBD
+
| rowspan="6" |I/O
−
| rowspan="6" |TBD
+
| rowspan="6" |
−
| rowspan="6" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI5_MCLK
 
|AUDIOMIX_SAI5_MCLK
Line 3,054: Line 3,081:
 
| rowspan="6" |J1.168
 
| rowspan="6" |J1.168
 
| rowspan="6" |SAI5_RXC
 
| rowspan="6" |SAI5_RXC
 +
| rowspan="6" |CPU.
 
| rowspan="6" |TBD
 
| rowspan="6" |TBD
−
| rowspan="6" |TBD
+
| rowspan="6" |NVCC_3V3
−
| rowspan="6" |TBD
+
| rowspan="6" |I/O
−
| rowspan="6" |TBD
+
| rowspan="6" |
−
| rowspan="6" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI5_RX_BCLK
 
|AUDIOMIX_SAI5_RX_BCLK
Line 3,080: Line 3,107:
 
| rowspan="6" |SAI5_RXD0//
 
| rowspan="6" |SAI5_RXD0//
 
ISO_14443_LA
 
ISO_14443_LA
 +
| rowspan="6" |CPU.
 
| rowspan="6" |TBD
 
| rowspan="6" |TBD
−
| rowspan="6" |TBD
+
| rowspan="6" |NVCC_3V3
−
| rowspan="6" |TBD
+
| rowspan="6" |I/O
−
| rowspan="6" |TBD
+
| rowspan="6" |
−
| rowspan="6" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI5_RX_DATA[0]
 
|AUDIOMIX_SAI5_RX_DATA[0]
Line 3,106: Line 3,133:
 
| rowspan="7" |SAI5_RXD1//
 
| rowspan="7" |SAI5_RXD1//
 
ISO_14443_LB
 
ISO_14443_LB
 +
| rowspan="7" |CPU.
 
| rowspan="7" |TBD
 
| rowspan="7" |TBD
−
| rowspan="7" |TBD
+
| rowspan="7" |NVCC_3V3
−
| rowspan="7" |TBD
+
| rowspan="7" |I/O
−
| rowspan="7" |TBD
+
| rowspan="7" |
−
| rowspan="7" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI5_RX_DATA[1]
 
|AUDIOMIX_SAI5_RX_DATA[1]
Line 3,135: Line 3,162:
 
| rowspan="7" |SAI5_RXD2//
 
| rowspan="7" |SAI5_RXD2//
 
ISO_7816_CLK
 
ISO_7816_CLK
 +
| rowspan="7" |CPU.
 
| rowspan="7" |TBD
 
| rowspan="7" |TBD
−
| rowspan="7" |TBD
+
| rowspan="7" |NVCC_3V3
−
| rowspan="7" |TBD
+
| rowspan="7" |I/O
−
| rowspan="7" |TBD
+
| rowspan="7" |
−
| rowspan="7" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI5_RX_DATA[2]
 
|AUDIOMIX_SAI5_RX_DATA[2]
Line 3,164: Line 3,191:
 
| rowspan="7" |SAI5_RXD3//
 
| rowspan="7" |SAI5_RXD3//
 
ISO_7816_RST_N
 
ISO_7816_RST_N
 +
| rowspan="7" |CPU.
 
| rowspan="7" |TBD
 
| rowspan="7" |TBD
−
| rowspan="7" |TBD
+
| rowspan="7" |NVCC_3V3
−
| rowspan="7" |TBD
+
| rowspan="7" |I/O
−
| rowspan="7" |TBD
+
| rowspan="7" |
−
| rowspan="7" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI5_RX_DATA[3]
 
|AUDIOMIX_SAI5_RX_DATA[3]
Line 3,193: Line 3,220:
 
| rowspan="5" |SAI5_RXFS//
 
| rowspan="5" |SAI5_RXFS//
 
SE050_ENA
 
SE050_ENA
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
+
|Pin ALT-0
−
|Pin ALT-0
+
|AUDIOMIX_SAI5_RX_SYNC
−
|AUDIOMIX_SAI5_RX_SYNC
 
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
Line 3,225: Line 3,252:
 
| rowspan="4" |J1.182
 
| rowspan="4" |J1.182
 
| rowspan="4" |SAI1_MCLK
 
| rowspan="4" |SAI1_MCLK
 +
| rowspan="4" |CPU.
 
| rowspan="4" |TBD
 
| rowspan="4" |TBD
−
| rowspan="4" |TBD
+
| rowspan="4" |NVCC_3V3
−
| rowspan="4" |TBD
+
| rowspan="4" |I/O
−
| rowspan="4" |TBD
+
| rowspan="4" |
−
| rowspan="4" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI1_MCLK
 
|AUDIOMIX_SAI1_MCLK
Line 3,244: Line 3,271:
 
| rowspan="4" |J1.184
 
| rowspan="4" |J1.184
 
| rowspan="4" |SAI1_RXC
 
| rowspan="4" |SAI1_RXC
 +
| rowspan="4" |CPU.
 
| rowspan="4" |TBD
 
| rowspan="4" |TBD
−
| rowspan="4" |TBD
+
| rowspan="4" |NVCC_3V3
−
| rowspan="4" |TBD
+
| rowspan="4" |I/O
−
| rowspan="4" |TBD
+
| rowspan="4" |
−
| rowspan="4" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI1_RX_BCLK
 
|AUDIOMIX_SAI1_RX_BCLK
Line 3,263: Line 3,290:
 
| rowspan="5" |J1.186
 
| rowspan="5" |J1.186
 
| rowspan="5" |SAI1_RXD0
 
| rowspan="5" |SAI1_RXD0
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI1_RX_DATA[0]
 
|AUDIOMIX_SAI1_RX_DATA[0]
Line 3,285: Line 3,312:
 
| rowspan="4" |J1.188
 
| rowspan="4" |J1.188
 
| rowspan="4" |SAI1_RXD1
 
| rowspan="4" |SAI1_RXD1
 +
| rowspan="4" |CPU.
 
| rowspan="4" |TBD
 
| rowspan="4" |TBD
−
| rowspan="4" |TBD
+
| rowspan="4" |NVCC_3V3
−
| rowspan="4" |TBD
+
| rowspan="4" |I/O
−
| rowspan="4" |TBD
+
| rowspan="4" |
−
| rowspan="4" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI1_RX_DATA[1]
 
|AUDIOMIX_SAI1_RX_DATA[1]
Line 3,304: Line 3,331:
 
| rowspan="5" |J1.190
 
| rowspan="5" |J1.190
 
| rowspan="5" |SAI1_RXD2
 
| rowspan="5" |SAI1_RXD2
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI1_RX_DATA[2]
 
|AUDIOMIX_SAI1_RX_DATA[2]
Line 3,326: Line 3,353:
 
| rowspan="5" |J1.192
 
| rowspan="5" |J1.192
 
| rowspan="5" |SAI1_RXD3
 
| rowspan="5" |SAI1_RXD3
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI1_RX_DATA[3]
 
|AUDIOMIX_SAI1_RX_DATA[3]
Line 3,348: Line 3,375:
 
| rowspan="5" |J1.194
 
| rowspan="5" |J1.194
 
| rowspan="5" |SAI1_RXD4
 
| rowspan="5" |SAI1_RXD4
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI1_RX_DATA[4]
 
|AUDIOMIX_SAI1_RX_DATA[4]
Line 3,370: Line 3,397:
 
| rowspan="6" |J1.196
 
| rowspan="6" |J1.196
 
| rowspan="6" |SAI1_RXD5
 
| rowspan="6" |SAI1_RXD5
 +
| rowspan="6" |CPU.
 
| rowspan="6" |TBD
 
| rowspan="6" |TBD
−
| rowspan="6" |TBD
+
| rowspan="6" |NVCC_3V3
−
| rowspan="6" |TBD
+
| rowspan="6" |I/O
−
| rowspan="6" |TBD
+
| rowspan="6" |
−
| rowspan="6" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI1_RX_DATA[5]
 
|AUDIOMIX_SAI1_RX_DATA[5]
Line 3,395: Line 3,422:
 
| rowspan="5" |J1.198
 
| rowspan="5" |J1.198
 
| rowspan="5" |SAI1_RXD6
 
| rowspan="5" |SAI1_RXD6
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
+
|Pin ALT-0
−
|Pin ALT-0
 
 
|AUDIOMIX_SAI1_RX_DATA[6]
 
|AUDIOMIX_SAI1_RX_DATA[6]
 
|-
 
|-
Line 3,417: Line 3,444:
 
| rowspan="6" |J1.200
 
| rowspan="6" |J1.200
 
| rowspan="6" |SAI1_RXD7
 
| rowspan="6" |SAI1_RXD7
 +
| rowspan="6" |CPU.
 
| rowspan="6" |TBD
 
| rowspan="6" |TBD
−
| rowspan="6" |TBD
+
| rowspan="6" |NVCC_3V3
−
| rowspan="6" |TBD
+
| rowspan="6" |I/O
−
| rowspan="6" |TBD
+
| rowspan="6" |
−
| rowspan="6" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI1_RX_DATA[7]
 
|AUDIOMIX_SAI1_RX_DATA[7]
Line 3,442: Line 3,469:
 
| rowspan="3" |J1.202
 
| rowspan="3" |J1.202
 
| rowspan="3" |SAI1_RXFS
 
| rowspan="3" |SAI1_RXFS
 +
| rowspan="3" |CPU.
 
| rowspan="3" |TBD
 
| rowspan="3" |TBD
−
| rowspan="3" |TBD
+
| rowspan="3" |NVCC_3V3
−
| rowspan="3" |TBD
+
| rowspan="3" |I/O
−
| rowspan="3" |TBD
+
| rowspan="3" |
−
| rowspan="3" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI1_RX_SYNC
 
|AUDIOMIX_SAI1_RX_SYNC
Line 3,458: Line 3,485:
 
| rowspan="4" |J1.204
 
| rowspan="4" |J1.204
 
| rowspan="4" |SAI1_TXC
 
| rowspan="4" |SAI1_TXC
 +
| rowspan="4" |CPU.
 
| rowspan="4" |TBD
 
| rowspan="4" |TBD
−
| rowspan="4" |TBD
+
| rowspan="4" |NVCC_3V3
−
| rowspan="4" |TBD
+
| rowspan="4" |I/O
−
| rowspan="4" |TBD
+
| rowspan="4" |
−
| rowspan="4" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI1_TX_BCLK
 
|AUDIOMIX_SAI1_TX_BCLK
Line 3,477: Line 3,504:
 
| rowspan="4" |J1.206
 
| rowspan="4" |J1.206
 
| rowspan="4" |SAI1_TXD0
 
| rowspan="4" |SAI1_TXD0
 +
| rowspan="4" |CPU.
 
| rowspan="4" |TBD
 
| rowspan="4" |TBD
−
| rowspan="4" |TBD
+
| rowspan="4" |NVCC_3V3
−
| rowspan="4" |TBD
+
| rowspan="4" |I/O
−
| rowspan="4" |TBD
+
| rowspan="4" |
−
| rowspan="4" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI1_TX_DATA[0]
 
|AUDIOMIX_SAI1_TX_DATA[0]
Line 3,496: Line 3,523:
 
| rowspan="4" |J1.208
 
| rowspan="4" |J1.208
 
| rowspan="4" |SAI1_TXD1
 
| rowspan="4" |SAI1_TXD1
 +
| rowspan="4" |CPU.
 
| rowspan="4" |TBD
 
| rowspan="4" |TBD
−
| rowspan="4" |TBD
+
| rowspan="4" |NVCC_3V3
−
| rowspan="4" |TBD
+
| rowspan="4" |I/O
−
| rowspan="4" |TBD
+
| rowspan="4" |
−
| rowspan="4" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI1_TX_DATA[1]
 
|AUDIOMIX_SAI1_TX_DATA[1]
Line 3,515: Line 3,542:
 
| rowspan="4" |J1.210
 
| rowspan="4" |J1.210
 
| rowspan="4" |SAI1_TXD2
 
| rowspan="4" |SAI1_TXD2
 +
| rowspan="4" |CPU.
 
| rowspan="4" |TBD
 
| rowspan="4" |TBD
−
| rowspan="4" |TBD
+
| rowspan="4" |NVCC_3V3
−
| rowspan="4" |TBD
+
| rowspan="4" |I/O
−
| rowspan="4" |TBD
+
| rowspan="4" |
−
| rowspan="4" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI1_TX_DATA[2]
 
|AUDIOMIX_SAI1_TX_DATA[2]
Line 3,534: Line 3,561:
 
| rowspan="4" |J1.212
 
| rowspan="4" |J1.212
 
| rowspan="4" |SAI1_TXD3
 
| rowspan="4" |SAI1_TXD3
 +
| rowspan="4" |CPU.
 
| rowspan="4" |TBD
 
| rowspan="4" |TBD
−
| rowspan="4" |TBD
+
| rowspan="4" |NVCC_3V3
−
| rowspan="4" |TBD
+
| rowspan="4" |I/O
−
| rowspan="4" |TBD
+
| rowspan="4" |
−
| rowspan="4" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI1_TX_DATA[3]
 
|AUDIOMIX_SAI1_TX_DATA[3]
Line 3,553: Line 3,580:
 
| rowspan="5" |J1.214
 
| rowspan="5" |J1.214
 
| rowspan="5" |SAI1_TXD4
 
| rowspan="5" |SAI1_TXD4
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI1_TX_DATA[4]
 
|AUDIOMIX_SAI1_TX_DATA[4]
Line 3,575: Line 3,602:
 
| rowspan="5" |J1.216
 
| rowspan="5" |J1.216
 
| rowspan="5" |SAI1_TXD5
 
| rowspan="5" |SAI1_TXD5
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
+
|Pin ALT-0
−
|Pin ALT-0
+
|AUDIOMIX_SAI1_TX_DATA[5]
−
|AUDIOMIX_SAI1_TX_DATA[5]
 
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
Line 3,597: Line 3,624:
 
| rowspan="5" |J1.218
 
| rowspan="5" |J1.218
 
| rowspan="5" |SAI1_TXD6
 
| rowspan="5" |SAI1_TXD6
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI1_TX_DATA[6]
 
|AUDIOMIX_SAI1_TX_DATA[6]
Line 3,619: Line 3,646:
 
| rowspan="5" |J1.220
 
| rowspan="5" |J1.220
 
| rowspan="5" |SAI1_TXD7
 
| rowspan="5" |SAI1_TXD7
 +
| rowspan="5" |CPU.
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI1_TX_DATA[7]
 
|AUDIOMIX_SAI1_TX_DATA[7]
Line 3,641: Line 3,668:
 
| rowspan="4" |J1.222
 
| rowspan="4" |J1.222
 
| rowspan="4" |SAI1_TXFS
 
| rowspan="4" |SAI1_TXFS
 +
| rowspan="4" |CPU.
 
| rowspan="4" |TBD
 
| rowspan="4" |TBD
−
| rowspan="4" |TBD
+
| rowspan="4" |NVCC_3V3
−
| rowspan="4" |TBD
+
| rowspan="4" |I/O
−
| rowspan="4" |TBD
+
| rowspan="4" |
−
| rowspan="4" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|AUDIOMIX_SAI1_TX_SYNC
 
|AUDIOMIX_SAI1_TX_SYNC
Line 3,666: Line 3,693:
 
|
 
|
 
|
 
|
 +
|
 +
|-
 +
|J1.226
 +
 +
(TPM on board)
 +
|I2C1_SCL//
 +
 +
I2C_SCL_SE050
 +
|TPM.ISO 7816 IO2
 +
|16
 +
|TPM_VOUT
 +
|I/O
 +
|
 +
|TBD
 
|
 
|
 
|-
 
|-
 
| rowspan="4" |J1.226
 
| rowspan="4" |J1.226
−
| rowspan="4" |I2C1_SCL//
+
| rowspan="4" |I2C1_SCL//
−
I2C_SCL_SE050
+
I2C_SCL_SE050
−
| rowspan="4" |TBD
+
| rowspan="4" |CPU.I2C1_SCL
−
| rowspan="4" |TBD
+
| rowspan="4" |TBD
−
| rowspan="4" |TBD
+
| rowspan="4" |NVCC_3V3
−
| rowspan="4" |TBD
+
| rowspan="4" |I/O
−
| rowspan="4" |TBD
+
| rowspan="4" |
−
|Pin ALT-0
+
|Pin ALT-0
−
|I2C1_SCL
+
|I2C1_SCL
−
|-
+
|-
−
|Pin ALT-1
+
|Pin ALT-1
−
|ENET_QOS_MDC
+
|ENET_QOS_MDC
−
|-
+
|-
−
|Pin ALT-3
+
|Pin ALT-3
−
|ECSPI1_SCLK
+
|ECSPI1_SCLK
−
|-
+
|-
−
|Pin ALT-5
+
|Pin ALT-5
−
|GPIO5_IO[14]
+
|GPIO5_IO[14]
 +
|-
 +
|J1.228
 +
(TPM on board)
 +
|I2C1_SDA//
 +
 
 +
I2C_SDA_SE050
 +
|TPM.ISO 7816 IO1
 +
|3
 +
|TPM_VOUT
 +
|I/O
 +
|
 +
|TBD
 +
|
 
|-
 
|-
 
| rowspan="4" |J1.228
 
| rowspan="4" |J1.228
 
| rowspan="4" |I2C1_SDA//
 
| rowspan="4" |I2C1_SDA//
 
I2C_SDA_SE050
 
I2C_SDA_SE050
 +
| rowspan="4" |CPU.I2C1_SDA
 
| rowspan="4" |TBD
 
| rowspan="4" |TBD
−
| rowspan="4" |TBD
+
| rowspan="4" |NVCC_3V3
−
| rowspan="4" |TBD
+
| rowspan="4" |I/O
−
| rowspan="4" |TBD
+
| rowspan="4" |
−
| rowspan="4" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|I2C1_SDA
 
|I2C1_SDA
Line 3,710: Line 3,764:
 
| rowspan="6" |J1.230
 
| rowspan="6" |J1.230
 
| rowspan="6" |I2C2_SCL
 
| rowspan="6" |I2C2_SCL
 +
| rowspan="6" |CPU.I2C2_SCL
 
| rowspan="6" |TBD
 
| rowspan="6" |TBD
−
| rowspan="6" |TBD
+
| rowspan="6" |NVCC_3V3
−
| rowspan="6" |TBD
+
| rowspan="6" |I/O
−
| rowspan="6" |TBD
+
| rowspan="6" |
−
| rowspan="6" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|I2C2_SCL
 
|I2C2_SCL
Line 3,735: Line 3,789:
 
| rowspan="5" |J1.232
 
| rowspan="5" |J1.232
 
| rowspan="5" |I2C2_SDA
 
| rowspan="5" |I2C2_SDA
 +
| rowspan="5" |CPU.I2C2_SDA
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|I2C2_SDA
 
|I2C2_SDA
Line 3,757: Line 3,811:
 
| rowspan="5" |J1.234
 
| rowspan="5" |J1.234
 
| rowspan="5" |I2C3_SCL
 
| rowspan="5" |I2C3_SCL
 +
| rowspan="5" |CPU.I2C3_SCL
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|I2C3_SCL
 
|I2C3_SCL
Line 3,779: Line 3,833:
 
| rowspan="5" |J1.236
 
| rowspan="5" |J1.236
 
| rowspan="5" |I2C3_SDA
 
| rowspan="5" |I2C3_SDA
 +
| rowspan="5" |CPU.I2C3_SDA
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|I2C3_SDA
 
|I2C3_SDA
Line 3,801: Line 3,855:
 
| rowspan="5" |J1.238
 
| rowspan="5" |J1.238
 
| rowspan="5" |I2C4_SCL
 
| rowspan="5" |I2C4_SCL
 +
| rowspan="5" |CPU.I2C4_SCL
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|I2C4_SCL
 
|I2C4_SCL
Line 3,823: Line 3,877:
 
| rowspan="4" |J1.240
 
| rowspan="4" |J1.240
 
| rowspan="4" |I2C4_SDA
 
| rowspan="4" |I2C4_SDA
 +
| rowspan="4" |CPU.I2C4_SDA
 
| rowspan="4" |TBD
 
| rowspan="4" |TBD
−
| rowspan="4" |TBD
+
| rowspan="4" |NVCC_3V3
−
| rowspan="4" |TBD
+
| rowspan="4" |I/O
−
| rowspan="4" |TBD
+
| rowspan="4" |
−
| rowspan="4" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|I2C4_SDA
 
|I2C4_SDA
Line 3,852: Line 3,906:
 
| rowspan="3" |J1.244
 
| rowspan="3" |J1.244
 
| rowspan="3" |UART1_RXD
 
| rowspan="3" |UART1_RXD
 +
| rowspan="3" |CPU.UART1_RXD
 
| rowspan="3" |TBD
 
| rowspan="3" |TBD
−
| rowspan="3" |TBD
+
| rowspan="3" |NVCC_3V3
−
| rowspan="3" |TBD
+
| rowspan="3" |I/O
−
| rowspan="3" |TBD
+
| rowspan="3" |
−
| rowspan="3" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|UART1_RX
 
|UART1_RX
Line 3,868: Line 3,922:
 
| rowspan="3" |J1.246
 
| rowspan="3" |J1.246
 
| rowspan="3" |UART1_TXD
 
| rowspan="3" |UART1_TXD
 +
| rowspan="3" |CPU.UART1_TXD
 
| rowspan="3" |TBD
 
| rowspan="3" |TBD
−
| rowspan="3" |TBD
+
| rowspan="3" |NVCC_3V3
−
| rowspan="3" |TBD
+
| rowspan="3" |I/O
−
| rowspan="3" |TBD
+
| rowspan="3" |
−
| rowspan="3" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|UART1_TX
 
|UART1_TX
Line 3,884: Line 3,938:
 
| rowspan="4" |J1.248
 
| rowspan="4" |J1.248
 
| rowspan="4" |UART2_RXD
 
| rowspan="4" |UART2_RXD
 +
| rowspan="4" |CPU.UART2_RXD
 
| rowspan="4" |TBD
 
| rowspan="4" |TBD
−
| rowspan="4" |TBD
+
| rowspan="4" |NVCC_3V3
−
| rowspan="4" |TBD
+
| rowspan="4" |I/O
−
| rowspan="4" |TBD
+
| rowspan="4" |
−
| rowspan="4" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|UART2_RX
 
|UART2_RX
Line 3,903: Line 3,957:
 
| rowspan="4" |J1.250
 
| rowspan="4" |J1.250
 
| rowspan="4" |UART2_TXD
 
| rowspan="4" |UART2_TXD
 +
| rowspan="4" |CPU.UART2_TXD
 
| rowspan="4" |TBD
 
| rowspan="4" |TBD
−
| rowspan="4" |TBD
+
| rowspan="4" |NVCC_3V3
−
| rowspan="4" |TBD
+
| rowspan="4" |I/O
−
| rowspan="4" |TBD
+
| rowspan="4" |
−
| rowspan="4" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|UART2_TX
 
|UART2_TX
Line 3,922: Line 3,976:
 
| rowspan="6" |J1.252
 
| rowspan="6" |J1.252
 
| rowspan="6" |UART3_RXD
 
| rowspan="6" |UART3_RXD
 +
| rowspan="6" |CPU.UART3_RXD
 
| rowspan="6" |TBD
 
| rowspan="6" |TBD
−
| rowspan="6" |TBD
+
| rowspan="6" |NVCC_3V3
−
| rowspan="6" |TBD
+
| rowspan="6" |I/O
−
| rowspan="6" |TBD
+
| rowspan="6" |
−
| rowspan="6" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|UART3_RX
 
|UART3_RX
Line 3,947: Line 4,001:
 
| rowspan="6" |J1.254
 
| rowspan="6" |J1.254
 
| rowspan="6" |UART3_TXD
 
| rowspan="6" |UART3_TXD
 +
| rowspan="6" |CPU.UART3_TXD
 
| rowspan="6" |TBD
 
| rowspan="6" |TBD
−
| rowspan="6" |TBD
+
| rowspan="6" |NVCC_3V3
−
| rowspan="6" |TBD
+
| rowspan="6" |I/O
−
| rowspan="6" |TBD
+
| rowspan="6" |
−
| rowspan="6" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|UART3_TX
 
|UART3_TX
Line 3,972: Line 4,026:
 
| rowspan="6" |J1.256
 
| rowspan="6" |J1.256
 
| rowspan="6" |UART4_RXD
 
| rowspan="6" |UART4_RXD
 +
| rowspan="6" |CPU.UART4_RXD
 
| rowspan="6" |TBD
 
| rowspan="6" |TBD
−
| rowspan="6" |TBD
+
| rowspan="6" |NVCC_3V3
−
| rowspan="6" |TBD
+
| rowspan="6" |I/O
−
| rowspan="6" |TBD
+
| rowspan="6" |
−
| rowspan="6" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|UART4_RX
 
|UART4_RX
Line 3,997: Line 4,051:
 
| rowspan="5" |J1.258
 
| rowspan="5" |J1.258
 
| rowspan="5" |UART4_TXD
 
| rowspan="5" |UART4_TXD
 +
| rowspan="5" |CPU.UART4_TXD
 
| rowspan="5" |TBD
 
| rowspan="5" |TBD
−
| rowspan="5" |TBD
+
| rowspan="5" |NVCC_3V3
−
| rowspan="5" |TBD
+
| rowspan="5" |I/O
−
| rowspan="5" |TBD
+
| rowspan="5" |
−
| rowspan="5" |TBD
 
 
|Pin ALT-0
 
|Pin ALT-0
 
|UART4_TX
 
|UART4_TX

Revision as of 16:45, 2 February 2021

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History
Version Issue Date Notes
1.0.0 Jan 2021 First release


TBD: modificare la tabella seguente con le caratteristiche dei pin del SOM

TBD: modificare le due tabelle ODD e EVEN con la mappa completa dei pins

TBD: nella tabella naming conventions, inserire il codice dei vari IC presenti (PMIC, PHY ETH, ecc.)

Connectors and Pinout Table[edit | edit source]

Connectors description[edit | edit source]

In the following table are described all available connectors integrated on ORCA:

Connector name Connector Type Notes Carrier board counterpart
J1 SODIMM DDR4 edge connector 260 pin TE Connectivity 2309407-1

The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to ORCA pinout specifications. See the images below for reference:

File:ORCA-top.png
ORCA TOP view
File:ORCA-bottom.png
ORCA BOTTOM view

Pinout table naming conventions[edit | edit source]

This chapter contains the pinout description of the ORCA module, grouped in two tables (odd and even pins) that report the pin mapping of the TBD: connector type ORCA connector.

Each row in the pinout tables contains the following information:

Pin Reference to the connector pin
Pin Name Pin (signal) name on the ORCA connectors
Internal
connections 		Connections to the ORCA components
  • CPU.<x> : pin connected to CPU pad named <x>
  • PMIC.<x> : pin connected to the Power Manager IC PCA9450
  • LAN.<x> : pin connected to the LAN PHY KSZ9131
  • eMMC.<x>: pin connected to the flash eMMC
  • NOR.<x>: pin connected to the flash NOR
  • NAND.<x>: pin connected to the flash NAND
  • MTR: pin connected to voltage monitors
  • TPM: pin connected to TPM unit SE050
Ball/pin # Component ball/pin number connected to signal
Voltage I/O voltage levels
Type Pin type:
  • I = Input
  • O = Output
  • D = Differential
  • Z = High impedance
  • S = Power supply voltage
  • G = Ground
  • A = Analog signal
Notes Remarks on special pin characteristics
Pin MUX alternative functions Muxes:
  • Pin ALT-0
  • ...
  • Pin ALT-N

The number of functions depends on platform

Pinout Table ODD pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage domain Type Notes Alternative Functions
J1.1 DGND DGND - - G
J1.3 VIN_SOM INPUT VOLTAGE - 3.3VIN S
J1.5 VIN_SOM INPUT VOLTAGE - 3.3VIN S
J1.7 VIN_SOM INPUT VOLTAGE - 3.3VIN S
J1.9 VIN_SOM INPUT VOLTAGE - 3.3VIN S
J1.11 VIN_SOM INPUT VOLTAGE - 3.3VIN S
J1.13 VIN_SOM INPUT VOLTAGE - 3.3VIN S
J1.15 CPU_ONOFF CPU.ONOFF G22 NVCC_SNVS_1V8 I/O internal pull-up 100k to NVCC_SNVS_1V8
J1.17 CPU_PORn CPU.POR_B

PMIC.POR_B

J29

9

NVCC_SNVS_1V8 I/O internal pull-up 100k to NVCC_SNVS_1V8
J1.19 PMIC_ON_REQ

//VMON_RST

CPU.PMIC_ON_REQ

PMIC.PMIC_ON_REQ

F22

39

NVCC_SNVS_1V8 I/O optionally connected to

voltage monitor reset

J1.21 PMIC_RST_B PMIC.PMIC_RST_B 8 NVCC_SNVS_1V8 I/O internal pull-up 100k to NVCC_SNVS_1V8
J1.23 BOARD_PGOOD MTR.RESET_B 2 NVCC_3V3 O
J1.25 BOOT_MODE0 CPU.BOOT_MODE0 G10 NVCC_3V3 TBD internal 10k pull-up or pull-down

according to specific model

J1.27 BOOT_MODE1 CPU.BOOT_MODE1 F8 NVCC_3V3 TBD internal 10k pull-up or pull-down

according to specific model

J1.29 BOOT_MODE2 CPU.BOOT_MODE2 G8 NVCC_3V3 TBD internal 10k pull-up or pull-down

according to specific model

J1.31 DGND DGND - - G
J1.33 LVDS0_D3_N CPU.LVDS0_D3_N J28 - D
J1.35 LVDS0_D3_P CPU.LVDS0_D3_P H29 - D
J1.37 LVDS0_D2_N CPU.LVDS0_D2_N H28 - D
J1.39 LVDS0_D2_P CPU.LVDS0_D2_P G29 - D
J1.41 LVDS0_CLK_N CPU.LVDS0_CLK_N G28 - D
J1.43 LVDS0_CLK_P CPU.LVDS0_CLK_P F29 - D
J1.45 LVDS0_D1_N CPU.LVDS0_D1_N F28 - D
J1.47 LVDS0_D1_P CPU.LVDS0_D1_P E29 - D
J1.49 LVDS0_D0_N CPU.LVDS0_D0_N E28 - D
J1.51 LVDS0_D0_P CPU.LVDS0_D0_P D29 - D
J1.53 DGND DGND - - G
J1.55 LVDS1_D3_N CPU.LVDS1_D3_N D28 - D
J1.57 LVDS1_D3_P CPU.LVDS1_D3_P C29 - D
J1.59 LVDS1_D2_N CPU.LVDS1_D2_N C28 - D
J1.61 LVDS1_D2_P CPU.LVDS1_D2_P B29 - D
J1.63 LVDS1_CLK_N CPU.LVDS1_CLK_N B28 - D
J1.65 LVDS1_CLK_P CPU.LVDS1_CLK_P A28 - D
J1.67 LVDS1_D1_N CPU.LVDS1_D1_N B27 - D
J1.69 LVDS1_D1_P CPU.LVDS1_D1_P A27 - D
J1.71 LVDS1_D0_N CPU.LVDS1_D0_N B26 - D
J1.73 LVDS1_D0_P CPU.LVDS1_D0_P A26 - D
J1.75 DGND DGND - - G
J1.77 MIPI_CSI2_D0_P CPU.MIPI_CSI2_D0_P A25 - D
J1.79 MIPI_CSI2_D0_N CPU.MIPI_CSI2_D0_N B25 - D
J1.81 MIPI_CSI2_D1_P CPU.MIPI_CSI2_D1_P A24 - D
J1.83 MIPI_CSI2_D1_N CPU.MIPI_CSI2_D1_N B24 - D
J1.85 MIPI_CSI2_CLK_P CPU.MIPI_CSI2_CLK_P A23 - D
J1.87 MIPI_CSI2_CLK_N CPU.MIPI_CSI2_CLK_N B23 - D
J1.89 MIPI_CSI2_D2_P CPU.MIPI_CSI2_D2_P A22 - D
J1.91 MIPI_CSI2_D2_N CPU.MIPI_CSI2_D2_N B22 - D
J1.93 MIPI_CSI2_D3_P CPU.MIPI_CSI2_D3_P A21 - D
J1.95 MIPI_CSI2_D3_N CPU.MIPI_CSI2_D3_N B21 - D
J1.97 DGND DGND - - G
J1.99 MIPI_CSI1_D3_P CPU.MIPI_CSI1_D3_P D26 - D
J1.101 MIPI_CSI1_D3_N CPU.MIPI_CSI1_D3_N E26 - D
J1.103 MIPI_CSI1_D2_P CPU.MIPI_CSI1_D2_P D24 - D
J1.105 MIPI_CSI1_D2_N CPU.MIPI_CSI1_D2_N E24 - D
J1.107 MIPI_CSI1_CLK_P CPU.MIPI_CSI1_CLK_P D22 - D
J1.109 MIPI_CSI1_CLK_N CPU.MIPI_CSI1_CLK_N E22 - D
J1.111 MIPI_CSI1_D1_P CPU.MIPI_CSI1_D1_P D20 - D
J1.113 MIPI_CSI1_D1_N CPU.MIPI_CSI1_D1_N E20 - D
J1.115 MIPI_CSI1_D0_P CPU.MIPI_CSI1_D0_P D18 - D
J1.117 MIPI_CSI1_D0_N CPU.MIPI_CSI1_D0_N E18 - D
J1.119 DGND DGND - - G
J1.121 MIPI_DSI1_D3_P CPU.MIPI_DSI1_D3_P A20 - D
J1.123 MIPI_DSI1_D3_N CPU.MIPI_DSI1_D3_N B20 - D
J1.125 MIPI_DSI1_D2_P CPU.MIPI_DSI1_D2_P A19 - D
J1.127 MIPI_DSI1_D2_N CPU.MIPI_DSI1_D2_N B19 - D
J1.129 MIPI_DSI1_CLK_P CPU.MIPI_DSI1_CLK_P A18 - D
J1.131 MIPI_DSI1_CLK_N CPU.MIPI_DSI1_CLK_N B18 - D
J1.133 MIPI_DSI1_D1_P CPU.MIPI_DSI1_D1_P A17 - D
J1.135 MIPI_DSI1_D1_N CPU.MIPI_DSI1_D1_N B17 - D
J1.137 MIPI_DSI1_D0_P CPU.MIPI_DSI1_D0_P A16 - D
J1.139 MIPI_DSI1_D0_N CPU.MIPI_DSI1_D0_N B16 - D
J1.141 DGND DGND - - G
J1.143 JTAG_MOD CPU.JTAG_MOD G20 NVCC_3V3 I/O
J1.145 JTAG_TCK CPU.JTAG_TCK G18 NVCC_3V3 I/O
J1.147 JTAG_TDI CPU.JTAG_TDI G16 NVCC_3V3 I
J1.149 JTAG_TMS CPU.JTAG_TMS G14 NVCC_3V3 I/O
J1.151 JTAG_TDO CPU.JTAG_TDO F14 NVCC_3V3 O
J1.153 DGND DGND - - G
J1.155 PCIE_REF_PAD_CLK_P CPU.PCIE_REF_PAD_CLK_P D16 - D
J1.157 PCIE_REF_PAD_CLK_N CPU.PCIE_REF_PAD_CLK_N E16 - D
J1.159 PCIE_TXN_P CPU.PCIE_TXN_P A15 - D
J1.161 PCIE_TXN_N CPU.PCIE_TXN_N B15 - D
J1.163 PCIE_RXN_P CPU.PCIE_RXN_P A14 - D
J1.165 PCIE_RXN_N CPU.PCIE_RXN_N B14 - D
J1.167 DGND DGND - - G
J1.169 USB2_VBUS USB2_VBUS - - S See USB section for details (5-20V tolerance)
J1.171 USB2_ID CPU.USB2_ID E12 NVCC_3V3 I
J1.173 USB2_D_P CPU.USB2_D_P D14 - D
J1.175 USB2_D_N CPU.USB2_D_N E14 - D
J1.177 DGND DGND - - G
J1.179 USB2_TX_P CPU.USB2_TX_P A13 - D
J1.181 USB2_TX_N CPU.USB2_TX_N B13 - D
J1.183 USB2_RX_P CPU.USB2_RX_P A12 - D
J1.185 USB2_RX_N CPU.USB2_RX_N B12 - D
J1.187 DGND DGND - - G
J1.189 USB1_VBUS USB1_VBUS - - S See USB section for details (5-20V tolerance)
J1.191 USB1_ID CPOU.USB1_ID B11 NVCC_3V3 I
J1.193 USB1_D_P CPU.USB1_D_P D10 - D
J1.195 USB1_D_N CPU.USB1_D_N E10 - D
J1.197 DGND DGND - - G
J1.199 USB1_TX_P CPU.USB1_TX_P A10 - D
J1.201 USB1_TX_N CPU.USB1_TX_N B10 - D
J1.203 USB1_RX_P CPU.USB1_RX_P A9 - D
J1.205 USB1_RX_N CPU.USB1_RX_N B9 - D
J1.207 DGND DGND - - G
J1.209 GPIO1_IO08 CPU.GPIO1_IO08 A8 NVCC_3V3 I/O Pin ALT-0 GPIO1_IO08
Pin ALT-1 ENET_QOS_1588_EVENT0_IN
Pin ALT-2 PWM1_OUT
Pin ALT-3 ISP_PRELIGHT_TRIG_1
Pin ALT-4 ENET_QOS_1588_EVENT0_AUX_IN
Pin ALT-5 USDHC2_RESET_B
J1.211 GPIO1_IO11 CPU.GPIO1_IO11 D8 NVCC_3V3 I/O Pin ALT-0 GPIO1_IO11
Pin ALT-1 USB2_OTG_ID
Pin ALT-2 PWM2_OUT
Pin ALT-4 USDHC3_VSELECT
Pin ALT-5 CCM_PMIC_READY
J1.213 GPIO1_IO09 CPU.GPIO1_IO09 B8 NVCC_3V3 I/O Pin ALT-0 GPIO1_IO09
Pin ALT-1 ENET_QOS_1588_EVENT0_OUT
Pin ALT-2 PWM2_OUT
Pin ALT-3 ISP_SHUTTER_OPEN_1
Pin ALT-4 USDHC3_RESET_B
Pin ALT-5 SDMA2_EXT_EVENT00
J1.215 GPIO1_IO00 CPU.GPIO1_IO00 A7 NVCC_3V3 I/O Pin ALT-0 GPIO1_IO00
Pin ALT-1 CCM_ENET_PHY_REF_CLK_ROOT
Pin ALT-3 ISP_FL_TRIG_0
Pin ALT-6 CCM_EXT_CLK1
J1.217 GPIO1_IO01 CPU.GPIO1_IO01 E8 NVCC_3V3 I/O Pin ALT-0 GPIO1_IO01
Pin ALT-1 PWM1_OUT
Pin ALT-3 ISP_SHUTTER_TRIG_0
Pin ALT-6 CCM_EXT_CLK2
J1.219 GPIO1_IO10 CPU.GPIO1_IO10 B7 NVCC_3V3 I/O Pin ALT-0 GPIO1_IO10
Pin ALT-1 USB1_OTG_ID
Pin ALT-2 PWM3_OUT
J1.221 GPIO1_IO13 CPU.GPIO1_IO13 A6 NVCC_3V3 I/O Pin ALT-0 GPIO1_IO13
Pin ALT-1 TUSB1_OTG_OCBD
Pin ALT-5 PWM2_OUT
J1.223 GPIO1_IO12 CPU.GPIO1_IO12 A5 NVCC_3V3 I/O Pin ALT-0 GPIO1_IO12
Pin ALT-1 USB1_OTG_PWR
Pin ALT-5 SDMA2_EXT_EVENT01
J1.225 GPIO1_IO07 CPU.GPIO1_IO07 F6 NVCC_3V3 I/O Pin ALT-0 GPIO1_IO07
Pin ALT-1 ENET_QOS_MDIO
Pin ALT-3 ISP_FLASH_TRIG_1
Pin ALT-5 USDHC1_WP
Pin ALT-6 CCM_EXT_CLK4
J1.227 GPIO1_IO15 CPU.GPIO1_IO15 B5 NVCC_3V3 I/O Pin ALT-0 GPIO1_IO15
Pin ALT-1 USB2_OTG_OC
Pin ALT-4 USDHC3_WP
Pin ALT-5 PWM4_OUT
Pin ALT-6 CCM_CLKO2
J1.229 GPIO1_IO14 CPU.GPIO1_IO14 A4 NVCC_3V3 I/O Pin ALT-0 GPIO1_IO14
Pin ALT-1 USB2_OTG_PWR
Pin ALT-4 USDHC3_CD_B
Pin ALT-5 PWM3_OUT
Pin ALT-6 CCM_CLKO1
J1.231 GPIO1_IO05 CPU.GPIO1_IO05 B4 NVCC_3V3 I/O Pin ALT-0 GPIO1_IO05
Pin ALT-1 M7_NMI
Pin ALT-3 ISP_FL_TRIG_1
Pin ALT-6 CCM_PMIC_READY
J1.233 GPIO1_IO06 CPU.GPIO1_IO06 A3 NVCC_3V3 I/O Pin ALT-0 GPIO1_IO06
Pin ALT-1 ENET_QOS_MDC
Pin ALT-3 ISP_SHUTTER_TRIG_1
Pin ALT-5 USDHC1_CD_B
Pin ALT-6 CCM_EXT_CLK3
J1.235 DGND DGND - - G
J1.237 ETH0_TXRX3_M LAN.TXTRM_D 11 - D
J1.239 ETH0_TXRX3_P LAN.TXTRP_D 10 - D
J1.241 ETH0_TXRX2_M LAN.TXTRM_C 8 - D
J1.243 ETH0_TXRX2_P LAN.TXTRP_C 7 - D
J1.245 ETH0_TXRX1_M LAN.TXTRM_B 6 - D
J1.247 ETH0_TXRX1_P LAN.TXTRP_B 5 - D
J1.249 ETH0_TXRX0_M LAN.TXTRM_A 3 - D
J1.251 ETH0_TXRX0_P LAN.TXTRP_A 2 - D
J1.253 DGND DGND - - G
J1.255 ETH0_LED1 LAN.LED2 15 VDD_1V8 O Must be level translated if used @ 3V3

Internally pulled-up to 1.8V during bootstrap

J1.257 ETH0_LED2 LAN.LED1/PME_N1 17 VDD_1V8 O Must be level translated if used @ 3V3

Internally pulled-up to 1.8V during bootstrap

J1.259 DGND DGND - - G

Pinout Table EVEN pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage domain Type Notes Alternative Functions
J1.2 DGND DGND - - G
J1.4 VIN_SOM INPUT VOLTAGE - 3.3VIN S
J1.6 VIN_SOM INPUT VOLTAGE - 3.3VIN S
J1.8 VIN_SOM INPUT VOLTAGE - 3.3VIN S
J1.10 VIN_SOM INPUT VOLTAGE - 3.3VIN S
J1.12 VIN_SOM INPUT VOLTAGE - 3.3VIN S
J1.14 DGND DGND - - G
J1.16 SD1_CLK CPU. TBD NVCC_SD1 I/O Pin ALT-0 USDHC1_CLK
Pin ALT-1 ENET1_MDC
Pin ALT-3 I2C5_SCL
Pin ALT-4 UART1_TX
Pin ALT-5 GPIO2_IO[0]
J1.18 SD1_CMD CPU. TBD NVCC_SD1 I/O Pin ALT-0 USDHC1_CMD
Pin ALT-1 ENET1_MDIO
Pin ALT-3 I2C5_SDA
Pin ALT-4 UART1_RX
Pin ALT-5 GPIO2_IO[1]
J1.20 SD1_DATA0 CPU. TBD NVCC_SD1 I/O Pin ALT-0 USDHC1_DATA0
Pin ALT-1 ENET1_RGMII_TD1
Pin ALT-3 I2C6_SCL
Pin ALT-4 UART1_RTS_B
Pin ALT-5 GPIO2_IO[2]
J1.22 SD1_DATA1 CPU. TBD NVCC_SD1 I/O Pin ALT-0 USDHC1_DATA1
Pin ALT-1 ENET1_RGMII_TD0
Pin ALT-3 I2C6_SDA
Pin ALT-4 UART1_CTS_B
Pin ALT-5 GPIO2_IO[3]
J1.24 SD1_DATA2 CPU. TBD NVCC_SD1 I/O Pin ALT-0 USDHC1_DATA2
Pin ALT-1 ENET1_RGMII_RD0
Pin ALT-3 I2C4_SCL
Pin ALT-4 UART2_TX
Pin ALT-5 GPIO2_IO[4]
J1.26 SD1_DATA3 CPU. TBD NVCC_SD1 I/O Pin ALT-0 USDHC1_DATA3
Pin ALT-1 ENET1_RGMII_RD1
Pin ALT-3 I2C4_SDA
Pin ALT-4 UART2_RX
Pin ALT-5 GPIO2_IO[5]
J1.28 SD1_DATA4 CPU. TBD NVCC_SD1 I/O Pin ALT-0 USDHC1_DATA4
Pin ALT-1 ENET1_RGMII_TX_CTL
Pin ALT-3 I2C1_SCL
Pin ALT-4 UART2_RTS_B
Pin ALT-5 GPIO2_IO[6]
J1.30 SD1_DATA5 CPU. TBD NVCC_SD1 I/O Pin ALT-0 USDHC1_DATA5
Pin ALT-1 ENET1_TX_ER
Pin ALT-3 I2C1_SDA
Pin ALT-4 UART2_CTS_B
Pin ALT-5 GPIO2_IO[7]
J1.32 SD1_DATA6 CPU. TBD NVCC_SD1 I/O Pin ALT-0 USDHC1_DATA6
Pin ALT-1 FLEXSPI_B_DATA[2]
Pin ALT-2 USDHC3_DATA2
Pin ALT-3 FLEXSPI_A_DATA[6]
Pin ALT-4 ISP_PRELIGHT_TRIG_1
Pin ALT-5 GPIO3_IO[12]
J1.34 SD1_DATA7 CPU. TBD NVCC_SD1 I/O Pin ALT-0 USDHC1_DATA7
Pin ALT-1 ENET1_RX_ER
Pin ALT-3 I2C2_SDA
Pin ALT-4 UART3_RX
Pin ALT-5 GPIO2_IO[9]
J1.36 SD1_RESET_B CPU. TBD NVCC_SD1 I/O Pin ALT-0 USDHC1_RESET_B
Pin ALT-1 ENET1_TX_CLK
Pin ALT-3 I2C3_SCL
Pin ALT-4 UART3_RTS_B
Pin ALT-5 GPIO2_IO[10]
J1.38 SD1_STROBE CPU. TBD NVCC_SD1 I/O Pin ALT-0 USDHC1_STROBE
Pin ALT-3 I2C3_SDA
Pin ALT-4 UART3_CTS_B
Pin ALT-5 GPIO2_IO[11]
J1.40 DGND DGND - - G
J1.42 SD2_CD_B CPU. TBD NVCC_SD2 I/O Pin ALT-0 USDHC2_CD_B
Pin ALT-5 GPIO2_IO[12]
J1.44 SD2_CLK CPU. TBD NVCC_SD2 I/O Pin ALT-0 USDHC2_CLK
Pin ALT-2 ECSPI2_SCLK
Pin ALT-3 UART4_RX
Pin ALT-5 GPIO2_IO[13]
J1.46 SD2_CMD CPU. TBD NVCC_SD2 I/O Pin ALT-0 USDHC2_CMD
Pin ALT-2 ECSPI2_MOSI
Pin ALT-3 UART4_TX
Pin ALT-4 AUDIOMIX_CLK
Pin ALT-5 GPIO2_IO[14]
J1.48 SD2_DATA0 CPU. TBD NVCC_SD2 I/O Pin ALT-0 USDHC2_DATA0
Pin ALT-2 I2C4_SDA
Pin ALT-3 UART2_RX
Pin ALT-4 AUDIOMIX_BIT_STREAM[0]
Pin ALT-5 GPIO2_IO[15]
J1.50 SD2_DATA1 CPU. TBD NVCC_SD2 I/O Pin ALT-0 USDHC2_DATA1
Pin ALT-2 I2C4_SCL
Pin ALT-3 UART2_TX
Pin ALT-4 AUDIOMIX_BIT_STREAM[1]
Pin ALT-5 GPIO2_IO[16]
J1.52 SD2_DATA2 CPU. TBD NVCC_SD2 I/O Pin ALT-0 USDHC2_DATA2
Pin ALT-2 ECSPI2_SS0
Pin ALT-3 AUDIOMIX_SPDIF_OUT
Pin ALT-4 AUDIOMIX_BIT_STREAM[2]
Pin ALT-5 GPIO2_IO[17]
J1.54 SD2_DATA3 CPU. TBD NVCC_SD2 I/O Pin ALT-0 USDHC2_DATA3
Pin ALT-2 ECSPI2_MISO
Pin ALT-3 AUDIOMIX_SPDIF_IN
Pin ALT-4 AUDIOMIX_BIT_STREAM[3]
Pin ALT-5 GPIO2_IO[18]
Pin ALT-6 SRC_EARLY_RESET
J1.56 SD2_RESET_B CPU. TBD NVCC_SD2 I/O Pin ALT-0 USDHC2_RESET_B
Pin ALT-5 GPIO2_IO[19]
Pin ALT-6 SRC_SYSTEM_RESET
J1.58 SD2_WP CPU. TBD NVCC_SD2 I/O Pin ALT-0 USDHC2_WP
Pin ALT-5 GPIO2_IO[20]
Pin ALT-6 CORESIGHT_EVENTI
J1.58

(both NAND and

NOR on board)

SD2_WP CPU. TBD NVCC_SD2 O internal use for

NAND/NOR selection,

do not connect

J1.60 DGND DGND - - G
J1.62 CLKIN1 CPU. TBD NVCC_3V3 I
J1.64 CLKIN2 CPU. TBD NVCC_3V3 I
J1.66 DGND DGND - - G
J1.68 CLKOUT1 CPU. TBD NVCC_3V3 O
J1.70 CLKOUT2 CPU. TBD NVCC_3V3 O
J1.72 DGND DGND - - G
J1.74 HDMI_CEC CPU. TBD NVCC_3V3 I/O Pin ALT-0 HDMIMIX_EARC_CEC
Pin ALT-3 I2C6_SCL
Pin ALT-4 CAN2_TX
Pin ALT-5 GPIO3_IO[28]
J1.76 HDMI_DDC_SCL CPU. TBD NVCC_3V3 I/O Pin ALT-0 HDMIMIX_EARC_SCL
Pin ALT-3 I2C5_SCL
Pin ALT-4 CAN1_TX
Pin ALT-5 GPIO3_IO[26]
J1.78 HDMI_DDC_SDA CPU. TBD NVCC_3V3 I/O Pin ALT-0 HDMIMIX_EARC_SDA
Pin ALT-3 I2C5_SDA
Pin ALT-4 CAN1_RX
Pin ALT-5 GPIO3_IO[27]
J1.80 HDMI_HPD CPU. TBD NVCC_3V3 I/O Pin ALT-0 HDMIMIX_EARC_DC_HPD
Pin ALT-1 AUDIOMIX_EARC_HDMI_HPD_O
Pin ALT-3 I2C6_SDA
Pin ALT-4 CAN2_RX
Pin ALT-5 GPIO3_IO[29]
J1.82 DGND DGND - - G
J1.84 HDMI_TXC_N CPU. TBD - D
J1.86 HDMI_TXC_P CPU. TBD - D
J1.88 HDMI_TX0_N CPU. TBD - D
J1.90 HDMI_TX0_P CPU. TBD - D
J1.92 HDMI_TX1_N CPU. TBD - D
J1.94 HDMI_TX1_P CPU. TBD - D
J1.96 HDMI_TX2_N CPU. TBD - D
J1.98 HDMI_TX2_P CPU. TBD - D
J1.100 DGND DGND - - G
J1.102 EARC_P_UTIL CPU. TBD VDDA_1V8 D
J1.104 EARC_N_HPD CPU. TBD VDDA_1V8 D
J1.106 EARC_AUX CPU. TBD VDDA_1V8 I/O
J1.108 DGND DGND - - G
J1.110 ECSPI1_MISO CPU. TBD NVCC_3V3 I/O Pin ALT-0 ECSPI1_MISO
Pin ALT-1 UART3_CTS_B
Pin ALT-2 I2C2_SCL
Pin ALT-3 AUDIOMIX_SAI7_RX_DATA[0]
Pin ALT-5 GPIO5_IO[8]
J1.112 ECSPI1_MOSI CPU. TBD NVCC_3V3 I/O Pin ALT-0 ECSPI1_MOSI
Pin ALT-1 UART3_TX
Pin ALT-2 I2C1_SDA
Pin ALT-3 AUDIOMIX_SAI7_RX_BCLK
Pin ALT-5 GPIO5_IO[7]
J1.114 ECSPI1_SCLK CPU. TBD NVCC_3V3 I/O Pin ALT-0 ECSPI1_SCLK
Pin ALT-1 UART3_RX
Pin ALT-2 I2C1_SCL
Pin ALT-3 AUDIOMIX_SAI7_RX_SYNC
Pin ALT-5 GPIO5_IO[6]
J1.116 ECSPI1_SS0 CPU. TBD NVCC_3V3 I/O Pin ALT-0 ECSPI1_SS0
Pin ALT-1 UART3_RTS_B
Pin ALT-2 I2C2_SDA
Pin ALT-3 AUDIOMIX_SAI7_TX_SYNC
Pin ALT-5 GPIO5_IO[9]
J1.118 DGND DGND - - G
J1.120 ECSPI2_MISO CPU. TBD NVCC_3V3 I/O Pin ALT-0 ECSPI2_MISO
Pin ALT-1 UART4_CTS_B
Pin ALT-2 I2C4_SCL
Pin ALT-3 AUDIOMIX_SAI7_MCLK
Pin ALT-4 CCM_CLKO1
Pin ALT-5 GPIO5_IO[12]
J1.122 ECSPI2_MOSI CPU. TBD NVCC_3V3 I/O Pin ALT-0 ECSPI2_MOSI
Pin ALT-1 UART4_TX
Pin ALT-2 I2C3_SDA
Pin ALT-3 AUDIOMIX_SAI7_TX_DATA[0]
Pin ALT-5 GPIO5_IO[11]
J1.124 ECSPI2_SCLK CPU. TBD NVCC_3V3 I/O Pin ALT-0 ECSPI2_SCLK
Pin ALT-1 UART4_RX
Pin ALT-2 I2C3_SCL
Pin ALT-3 AUDIOMIX_SAI7_TX_BCLK
Pin ALT-5 GPIO5_IO[10]
J1.126 ECSPI2_SS0 CPU. TBD NVCC_3V3 I/O Pin ALT-0 ECSPI2_SS0
Pin ALT-1 UART4_RTS_B
Pin ALT-2 I2C4_SDA
Pin ALT-4 CCM_CLKO2
Pin ALT-5 GPIO5_IO[13]
J1.128 DGND DGND - - G
J1.130 SPDIF_EXT_CLK//

ISP_FL_TRIG_0

CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SPDIF_EXT_CLK
Pin ALT-1 PWM1_OUT
Pin ALT-3 GPT1_COMPARE3
Pin ALT-5 GPIO5_IO[5]
J1.132 SPDIF_RX//

ISP_SHUTTER_TRIG_0

CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SPDIF_IN
Pin ALT-1 PWM2_OUT
Pin ALT-2 I2C5_SDA
Pin ALT-3 GPT1_COMPARE2
Pin ALT-4 CAN1_RX
Pin ALT-5 GPIO5_IO[4]
J1.134 SPDIF_TX//

ISP_FLASH_TRIG_0

CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SPDIF_OUT
Pin ALT-1 PWM3_OUT
Pin ALT-2 I2C5_SCL
Pin ALT-3 GPT1_COMPARE1
Pin ALT-4 CAN1_TX
Pin ALT-5 GPIO5_IO[3]
J1.136 DGND DGND - - G
J1.138 SAI2_MCLK CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI2_MCLK
Pin ALT-1 AUDIOMIX_SAI5_MCLK
Pin ALT-2 ENET_QOS_1588_EVENT3_IN
Pin ALT-3 CAN2_RX
Pin ALT-4 ENET_QOS_1588_EVENT3_AUX_IN
Pin ALT-5 GPIO4_IO[27]
Pin ALT-6 AUDIOMIX_SAI3_MCLK
J1.140 SAI2_RXC CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI2_RX_BCLK
Pin ALT-1 AUDIOMIX_SAI5_TX_BCLK
Pin ALT-3 CAN1_TX
Pin ALT-4 UART1_RX
Pin ALT-5 GPIO4_IO[22]
Pin ALT-6 AUDIOMIX_BIT_STREAM[1]
J1.142 SAI2_RXD0 CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI2_RX_DATA[0]
Pin ALT-1 AUDIOMIX_SAI5_TX_DATA[0]
Pin ALT-2 ENET_QOS_1588_EVENT2_OUT
Pin ALT-3 AUDIOMIX_SAI2_TX_DATA[1]
Pin ALT-4 UART1_RTS_B
Pin ALT-5 GPIO4_IO[23]
Pin ALT-6 AUDIOMIX_PDM_BIT_STREAM[3]
J1.144 SAI2_RXFS CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI2_RX_SYNC
Pin ALT-1 AUDIOMIX_SAI5_TX_SYNC
Pin ALT-2 AUDIOMIX_SAI5_TX_DATA[1]
Pin ALT-3 AUDIOMIX_SAI2_RX_DATA[1]
Pin ALT-4 UART1_TX
Pin ALT-5 GPIO4_IO[21]
Pin ALT-6 AUDIOMIX_BIT_STREAM[2]
J1.146 SAI2_TXC CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI2_TX_BCLK
Pin ALT-1 AUDIOMIX_SAI5_TX_DATA[2]
Pin ALT-3 CAN1_RX
Pin ALT-5 GPIO4_IO[25]
Pin ALT-6 AUDIOMIX_BIT_STREAM[1]
J1.148 SAI2_TXD0 CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI2_TX_DATA[0]
Pin ALT-1 AUDIOMIX_SAI5_TX_DATA[3]
Pin ALT-2 ENET_QOS_1588_EVENT2_IN
Pin ALT-3 CAN2_TX
Pin ALT-4 ENET_QOS_1588_EVENT2_AUX_IN
Pin ALT-5 GPIO4_IO[26]
J1.150 SAI2_TXFS CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI2_TX_SYNC
Pin ALT-1 AUDIOMIX_SAI5_TX_DATA[1]
Pin ALT-2 ENET_QOS_1588_EVENT3_OUT
Pin ALT-3 AUDIOMIX_SAI2_TX_DATA[1]
Pin ALT-4 UART1_CTS_B
Pin ALT-5 GPIO4_IO[24]
Pin ALT-6 AUDIOMIX_PDM_BIT_STREAM[2]
J1.152 SAI3_MCLK//

ISP_PRELIGHT_TRIG_0

CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI3_MCLK
Pin ALT-1 PWM4_OUT
Pin ALT-2 AUDIOMIX_SAI5_MCLK
Pin ALT-4 AUDIOMIX_SPDIF_OUT
Pin ALT-5 GPIO5_IO[2]
Pin ALT-6 AUDIOMIX_SPDIF_IN
J1.154 SAI3_RXC//

ISP_SHUTTER_OPEN_0

CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI3_RX_BCLK
Pin ALT-1 AUDIOMIX_SAI2_RX_DATA[2]
Pin ALT-2 AUDIOMIX_SAI5_RX_BCLK
Pin ALT-3 GPT1_CLK
Pin ALT-4 UART2_CTS_B
Pin ALT-5 GPIO4_IO[29]
Pin ALT-6 AUDIOMIX_CLK
J1.156 SAI3_RXD//

ISP_FL_TRIG_1

CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI3_RX_DATA[0]
Pin ALT-1 AUDIOMIX_SAI2_RX_DATA[3]
Pin ALT-2 AUDIOMIX_SAI5_RX_DATA[0]
Pin ALT-4 UART2_RTS_B
Pin ALT-5 GPIO4_IO[30]
Pin ALT-6 AUDIOMIX_BIT_STREAM[1]
J1.158 SAI3_RXFS//

ISP_SHUTTER_TRIG_1

CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI3_RX_SYNC
Pin ALT-1 AUDIOMIX_SAI2_RX_DATA[1]
Pin ALT-2 AUDIOMIX_SAI5_RX_SYNC
Pin ALT-3 AUDIOMIX_SAI3_RX_DATA[1]
Pin ALT-4 AUDIOMIX_SPDIF1_IN
Pin ALT-5 GPIO4_IO[28]
Pin ALT-6 AUDIOMIX_PDM_BIT_STREAM[0]
J1.160 SAI3_TXC//

ISP_FLASH_TRIG_1

CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI3_TX_BCLK
Pin ALT-1 AUDIOMIX_SAI2_TX_DATA[2]
Pin ALT-2 AUDIOMIX_SAI5_RX_DATA[2]
Pin ALT-3 GPT1_CAPTURE1
Pin ALT-4 UART2_TX
Pin ALT-5 GPIO5_IO[0]
Pin ALT-6 AUDIOMIX_PDM_BIT_STREAM[2]
J1.162 SAI3_TXD//

ISP_PRELIGHT_TRIG_1

CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI3_TX_DATA[0]
Pin ALT-1 AUDIOMIX_SAI2_TX_DATA[3]
Pin ALT-2 AUDIOMIX_SAI5_RX_DATA[3]
Pin ALT-3 GPT1_CAPTURE2
Pin ALT-4 AUDIOMIX_SPDIF_EXT_CLK
Pin ALT-5 GPIO5_IO[1]
Pin ALT-6 SRC_BOOT_MODE[5]
J1.164 SAI3_TXFS//

ISP_SHUTTER_OPEN_1

CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI3_TX_SYNC
Pin ALT-1 AUDIOMIX_SAI2_TX_DATA[1]
Pin ALT-2 AUDIOMIX_SAI5_RX_DATA[1]
Pin ALT-3 AUDIOMIX_SAI3_TX_DATA[1]
Pin ALT-4 UART2_RX
Pin ALT-5 GPIO4_IO[31]
Pin ALT-6 AUDIOMIX_PDM_BIT_STREAM[3]
J1.166 SAI5_MCLK CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI5_MCLK
Pin ALT-1 AUDIOMIX_SAI1_TX_BCLK
Pin ALT-2 PWM1_OUT
Pin ALT-3 I2C5_SDA
Pin ALT-5 GPIO3_IO[25]
Pin ALT-6 CAN2_RX
J1.168 SAI5_RXC CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI5_RX_BCLK
Pin ALT-1 AUDIOMIX_SAI1_TX_DATA[1]
Pin ALT-2 PWM3_OUT
Pin ALT-3 I2C6_SDA
Pin ALT-4 AUDIOMIX_CLK
Pin ALT-5 GPIO3_IO[20]
J1.170 SAI5_RXD0//

ISO_14443_LA

CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI5_RX_DATA[0]
Pin ALT-1 AUDIOMIX_SAI1_TX_DATA[2]
Pin ALT-2 PWM2_OUT
Pin ALT-3 I2C5_SCL
Pin ALT-4 AUDIOMIX_BIT_STREAM[0]
Pin ALT-5 GPIO3_IO[21]
J1.172 SAI5_RXD1//

ISO_14443_LB

CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI5_RX_DATA[1]
Pin ALT-1 AUDIOMIX_SAI1_TX_DATA[3]
Pin ALT-2 AUDIOMIX_SAI1_TX_SYNC
Pin ALT-3 AUDIOMIX_SAI5_TX_SYNC
Pin ALT-4 AUDIOMIX_BIT_STREAM[1]
Pin ALT-5 GPIO3_IO[22]
Pin ALT-6 CAN1_TX
J1.174 SAI5_RXD2//

ISO_7816_CLK

CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI5_RX_DATA[2]
Pin ALT-1 AUDIOMIX_SAI1_TX_DATA[4]
Pin ALT-2 AUDIOMIX_SAI1_TX_SYNC
Pin ALT-3 AUDIOMIX_SAI5_TX_BCLK
Pin ALT-4 AUDIOMIX_BIT_STREAM[2]
Pin ALT-5 GPIO3_IO[23]
Pin ALT-6 CAN1_RX
J1.176 SAI5_RXD3//

ISO_7816_RST_N

CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI5_RX_DATA[3]
Pin ALT-1 AUDIOMIX_SAI1_TX_DATA[5]
Pin ALT-2 AUDIOMIX_SAI1_TX_SYNC
Pin ALT-3 AUDIOMIX_SAI5_TX_DATA[0]
Pin ALT-4 AUDIOMIX_PDM_BIT_STREAM[3]
Pin ALT-5 GPIO3_IO[24]
Pin ALT-6 CAN2_TX
J1.178 SAI5_RXFS//

SE050_ENA

CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI5_RX_SYNC
Pin ALT-1 AUDIOMIX_SAI1_TX_DATA[0]
Pin ALT-2 PWM4_OUT
Pin ALT-3 I2C6_SCL
Pin ALT-5 GPIO3_IO[19]
J1.180 DGND DGND - - G
J1.182 SAI1_MCLK CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI1_MCLK
Pin ALT-1 AUDIOMIX_SAI1_TX_BCLK
Pin ALT-4 ENET1_TX_CLK
Pin ALT-5 GPIO4_IO[20]
J1.184 SAI1_RXC CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI1_RX_BCLK
Pin ALT-1 AUDIOMIX_PDM_CLK
Pin ALT-4 ENET1_1588_EVENT0_OUT
Pin ALT-5 GPIO4_IO[1]
J1.186 SAI1_RXD0 CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI1_RX_DATA[0]
Pin ALT-2 AUDIOMIX_SAI1_TX_DATA[1]
Pin ALT-3 AUDIOMIX_PDM_BIT_STREAM[0]
Pin ALT-4 ENET1_1588_EVENT1_IN
Pin ALT-5 GPIO4_IO[2]
J1.188 SAI1_RXD1 CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI1_RX_DATA[1]
Pin ALT-3 AUDIOMIX_PDM_BIT_STREAM[1]
Pin ALT-4 ENET1_1588_EVENT1_OUT
Pin ALT-5 GPIO4_IO[3]
J1.190 SAI1_RXD2 CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI1_RX_DATA[2]
Pin ALT-1 AUDIOMIX_SAI5_RX_DATA[2]
Pin ALT-3 AUDIOMIX_BIT_STREAM[2]
Pin ALT-4 ENET1_MDC
Pin ALT-5 GPIO4_IO[4]
J1.192 SAI1_RXD3 CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI1_RX_DATA[3]
Pin ALT-1 AUDIOMIX_SAI5_RX_DATA[3]
Pin ALT-3 AUDIOMIX_BIT_STREAM[3]
Pin ALT-4 ENET1_MDIO
Pin ALT-5 GPIO4_IO[5]
J1.194 SAI1_RXD4 CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI1_RX_DATA[4]
Pin ALT-1 AUDIOMIX_SAI6_TX_BCLK
Pin ALT-2 AUDIOMIX_SAI6_RX_BCLK
Pin ALT-4 ENET1_RGMII_RD0
Pin ALT-5 GPIO4_IO[6]
J1.196 SAI1_RXD5 CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI1_RX_DATA[5]
Pin ALT-1 AUDIOMIX_SAI6_TX_DATA[0]
Pin ALT-2 AUDIOMIX_SAI6_RX_DATA[0]
Pin ALT-3 AUDIOMIX_SAI1_RX_SYNC
Pin ALT-4 ENET1_RGMII_RD1
Pin ALT-5 GPIO4_IO[7]
J1.198 SAI1_RXD6 CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI1_RX_DATA[6]
Pin ALT-1 AUDIOMIX_SAI6_TX_SYNC
Pin ALT-2 AUDIOMIX_SAI6_RX_SYNC
Pin ALT-4 ENET1_RGMII_RD2
Pin ALT-5 GPIO4_IO[8]
J1.200 SAI1_RXD7 CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI1_RX_DATA[7]
Pin ALT-1 AUDIOMIX_SAI6_MCLK
Pin ALT-2 AUDIOMIX_SAI1_TX_SYNC
Pin ALT-3 AUDIOMIX_SAI1_TX_DATA[4]
Pin ALT-4 ENET1_RGMII_RD3
Pin ALT-5 GPIO4_IO[9]
J1.202 SAI1_RXFS CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI1_RX_SYNC
Pin ALT-4 ENET1_1588_EVENT0_IN
Pin ALT-5 GPIO4_IO[0]
J1.204 SAI1_TXC CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI1_TX_BCLK
Pin ALT-1 AUDIOMIX_SAI5_TX_BCLK
Pin ALT-4 ENET1_RGMII_RXC
Pin ALT-5 GPIO4_IO[11]
J1.206 SAI1_TXD0 CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI1_TX_DATA[0]
Pin ALT-1 AUDIOMIX_SAI5_TX_DATA[0]
Pin ALT-4 ENET1_RGMII_TD0
Pin ALT-5 GPIO4_IO[12]
J1.208 SAI1_TXD1 CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI1_TX_DATA[1]
Pin ALT-1 AUDIOMIX_SAI5_TX_DATA[1]
Pin ALT-4 ENET1_RGMII_TD1
Pin ALT-5 GPIO4_IO[13]
J1.210 SAI1_TXD2 CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI1_TX_DATA[2]
Pin ALT-1 AUDIOMIX_SAI5_TX_DATA[2]
Pin ALT-4 ENET1_RGMII_TD2
Pin ALT-5 GPIO4_IO[14]
J1.212 SAI1_TXD3 CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI1_TX_DATA[3]
Pin ALT-1 AUDIOMIX_SAI5_TX_DATA[3]
Pin ALT-4 ENET1_RGMII_TD3
Pin ALT-5 GPIO4_IO[15]
J1.214 SAI1_TXD4 CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI1_TX_DATA[4]
Pin ALT-1 AUDIOMIX_SAI6_RX_BCLK
Pin ALT-2 AUDIOMIX_SAI6_TX_BCLK
Pin ALT-4 ENET1_RGMII_TX_CTL
Pin ALT-5 GPIO4_IO[16]
J1.216 SAI1_TXD5 CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI1_TX_DATA[5]
Pin ALT-1 AUDIOMIX_SAI6_RX_DATA[0]
Pin ALT-2 AUDIOMIX_SAI6_TX_DATA[0]
Pin ALT-4 ENET1_RGMII_TXC
Pin ALT-5 GPIO4_IO[17]
J1.218 SAI1_TXD6 CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI1_TX_DATA[6]
Pin ALT-1 AUDIOMIX_SAI6_RX_SYNC
Pin ALT-2 AUDIOMIX_SAI6_TX_SYNC
Pin ALT-4 ENET1_RX_ER
Pin ALT-5 GPIO4_IO[18]
J1.220 SAI1_TXD7 CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI1_TX_DATA[7]
Pin ALT-1 AUDIOMIX_SAI6_MCLK
Pin ALT-3 AUDIOMIX_CLK
Pin ALT-4 ENET1_TX_ER
Pin ALT-5 GPIO4_IO[19]
J1.222 SAI1_TXFS CPU. TBD NVCC_3V3 I/O Pin ALT-0 AUDIOMIX_SAI1_TX_SYNC
Pin ALT-1 AUDIOMIX_SAI5_TX_SYNC
Pin ALT-4 ENET1_RGMII_RX_CTL
Pin ALT-5 GPIO4_IO[10]
J1.224 DGND DGND - - G
J1.226

(TPM on board)

I2C1_SCL//

I2C_SCL_SE050

TPM.ISO 7816 IO2 16 TPM_VOUT I/O TBD
J1.226 I2C1_SCL//

I2C_SCL_SE050

CPU.I2C1_SCL TBD NVCC_3V3 I/O Pin ALT-0 I2C1_SCL
Pin ALT-1 ENET_QOS_MDC
Pin ALT-3 ECSPI1_SCLK
Pin ALT-5 GPIO5_IO[14]
J1.228

(TPM on board)

I2C1_SDA//

I2C_SDA_SE050

TPM.ISO 7816 IO1 3 TPM_VOUT I/O TBD
J1.228 I2C1_SDA//

I2C_SDA_SE050

CPU.I2C1_SDA TBD NVCC_3V3 I/O Pin ALT-0 I2C1_SDA
Pin ALT-1 ENET_QOS_MDIO
Pin ALT-3 ECSPI1_MOSI
Pin ALT-5 GPIO5_IO[15]
J1.230 I2C2_SCL CPU.I2C2_SCL TBD NVCC_3V3 I/O Pin ALT-0 I2C2_SCL
Pin ALT-1 ENET_QOS_1588_EVENT1_IN
Pin ALT-2 USDHC3_CD_B
Pin ALT-3 ECSPI1_MISO
Pin ALT-4 ENET_QOS_1588_EVENT1_AUX_IN
Pin ALT-5 GPIO5_IO[16]
J1.232 I2C2_SDA CPU.I2C2_SDA TBD NVCC_3V3 I/O Pin ALT-0 I2C2_SDA
Pin ALT-1 ENET_QOS_1588_EVENT1_OUT
Pin ALT-2 USDHC3_WP
Pin ALT-3 ECSPI1_SS0
Pin ALT-5 GPIO5_IO[17]
J1.234 I2C3_SCL CPU.I2C3_SCL TBD NVCC_3V3 I/O Pin ALT-0 I2C3_SCL
Pin ALT-1 PWM4_OUT
Pin ALT-2 GPT2_CLK
Pin ALT-3 ECSPI2_SCLK
Pin ALT-5 GPIO5_IO[18]
J1.236 I2C3_SDA CPU.I2C3_SDA TBD NVCC_3V3 I/O Pin ALT-0 I2C3_SDA
Pin ALT-1 PWM3_OUT
Pin ALT-2 GPT3_CLK
Pin ALT-3 ECSPI2_MOSI
Pin ALT-5 GPIO5_IO[19]
J1.238 I2C4_SCL CPU.I2C4_SCL TBD NVCC_3V3 I/O Pin ALT-0 I2C4_SCL
Pin ALT-1 PWM2_OUT
Pin ALT-2 PCIE_CLKREQ_B
Pin ALT-3 ECSPI2_MISO
Pin ALT-5 GPIO5_IO[20]
J1.240 I2C4_SDA CPU.I2C4_SDA TBD NVCC_3V3 I/O Pin ALT-0 I2C4_SDA
Pin ALT-1 PWM1_OUT
Pin ALT-3 ECSPI2_SS0
Pin ALT-5 GPIO5_IO[21]
J1.242 DGND DGND - - G
J1.244 UART1_RXD CPU.UART1_RXD TBD NVCC_3V3 I/O Pin ALT-0 UART1_RX
Pin ALT-1 ECSPI3_SCLK
Pin ALT-5 GPIO5_IO[22]
J1.246 UART1_TXD CPU.UART1_TXD TBD NVCC_3V3 I/O Pin ALT-0 UART1_TX
Pin ALT-1 ECSPI3_MOSI
Pin ALT-5 GPIO5_IO[23]
J1.248 UART2_RXD CPU.UART2_RXD TBD NVCC_3V3 I/O Pin ALT-0 UART2_RX
Pin ALT-1 ECSPI3_MISO
Pin ALT-3 GPT1_COMPARE3
Pin ALT-5 GPIO5_IO[24]
J1.250 UART2_TXD CPU.UART2_TXD TBD NVCC_3V3 I/O Pin ALT-0 UART2_TX
Pin ALT-1 ECSPI3_SS0
Pin ALT-3 GPT1_COMPARE2
Pin ALT-5 GPIO5_IO[25]
J1.252 UART3_RXD CPU.UART3_RXD TBD NVCC_3V3 I/O Pin ALT-0 UART3_RX
Pin ALT-1 UART1_CTS_B
Pin ALT-2 USDHC3_RESET_B
Pin ALT-3 GPT1_CAPTURE2
Pin ALT-4 CAN2_TX
Pin ALT-5 GPIO5_IO[26]
J1.254 UART3_TXD CPU.UART3_TXD TBD NVCC_3V3 I/O Pin ALT-0 UART3_TX
Pin ALT-1 UART1_RTS_B
Pin ALT-2 USDHC3_VSELECT
Pin ALT-3 GPT1_CLK
Pin ALT-4 CAN2_RX
Pin ALT-5 GPIO5_IO[27]
J1.256 UART4_RXD CPU.UART4_RXD TBD NVCC_3V3 I/O Pin ALT-0 UART4_RX
Pin ALT-1 UART2_CTS_B
Pin ALT-2 PCIE_CLKREQ_B
Pin ALT-3 GPT1_COMPARE1
Pin ALT-4 I2C6_SCL
Pin ALT-5 GPIO5_IO[28]
J1.258 UART4_TXD CPU.UART4_TXD TBD NVCC_3V3 I/O Pin ALT-0 UART4_TX
Pin ALT-1 UART2_RTS_B
Pin ALT-3 GPT1_CAPTURE1
Pin ALT-4 I2C6_SDA
Pin ALT-5 GPIO5_IO[29]
J1.260 DGND DGND - - G
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