Difference between revisions of "ORCA SOM/ORCA Hardware/Peripherals/PCI Express"
< ORCA SOM | ORCA Hardware
| Line 15: | Line 15: | ||
<section end="History" /> | <section end="History" /> | ||
<section begin="Body" /> | <section begin="Body" /> | ||
| − | |||
| − | |||
==Peripheral PCI Express == | ==Peripheral PCI Express == | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
<section begin="Body" /> | <section begin="Body" /> | ||
| Line 45: | Line 37: | ||
The Pin mapping is described in the [[ORCA SOM/ORCA Hardware/Pinout_Table | Pinout table section]] | The Pin mapping is described in the [[ORCA SOM/ORCA Hardware/Pinout_Table | Pinout table section]] | ||
| − | |||
---- | ---- | ||
[[Category:ORCA]] | [[Category:ORCA]] | ||
Revision as of 15:26, 13 December 2021
| HOME | SOMs | SBCs | ToloMEO Embedded Assistant |  GET A QUOTE
|
 ONLINE HELPDESK
|
| Roadmap | IoT Services | ML/AI services | Embedded Design Services |
| History | |||
|---|---|---|---|
| Version | Issue Date | Notes | |
| 1.0.0 | Feb 2021 | First release | |
Peripheral PCI Express[edit | edit source]
PCI Express (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards.
Description[edit | edit source]
The PCI Express interface available on ORCA is based on iMX8MPlus SoC.
The PCI Express interface supports the following standards and features:
- two PCIe PHY ports (1-lane each)
- up to 8.0 Gbps data rate
- complies to PCI Express Gen3 specification
- 8B/10B Encoding / Decoding
- Supports Spread Spectrum Clocking in Transmitter and Receiver
Pin mapping[edit | edit source]
The Pin mapping is described in the Pinout table section
