ORCA SOM/ORCA Hardware/Peripherals/NPU
< ORCA SOM | ORCA HardwareRevision as of 10:13, 4 February 2021 by U0016 (talk | contribs) (Created page with "<section begin="History" /> {| style="border-collapse:collapse; " ! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History |- ! style="bo...")
| HOME | SOMs | SBCs | ToloMEO Embedded Assistant |  GET A QUOTE
|
 ONLINE HELPDESK
|
| Roadmap | IoT Services | ML/AI services | Embedded Design Services |
| History | |||
|---|---|---|---|
| Version | Issue Date | Notes | |
| 1.0.0 | Feb 2021 | First release | |
Peripheral NPUEdit
The Neural Processign Unit (NPU) available on ORCA is based on iMX8MPlus SoC.
DescriptionEdit
The Neural Processing Unit (NPU) core accelerates vision image processing functions and provides enhanced performance for real-time use cases with hardware support for the OpenVX API.
Key features of the NPU block include:
- OpenVX 1.2 compliance, including extensions
- Convolutional Neural Network acceleration
- IEEE 32-bit floating-point pipeline in PPU shaders.
- Ultra-threaded parallel processing unit
- Low bandwidth at both high and low data rates
- Low CPU loading
- MMU functionality supported
- Performance Counters for DMA Profiling
- Data transfers between Neural Network Engines and the Parallel Processing Unit, with SRAM as local storage
- Neural Network Engine and Parallel Processing Unit synchronization with hardware semaphore