Difference between revisions of "ORCA SOM/ORCA Hardware/Peripherals/NPU"
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! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History | ! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History | ||
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==Peripheral NPU == | ==Peripheral NPU == | ||
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* Data transfers between Neural Network Engines and the Parallel Processing Unit, with SRAM as local storage | * Data transfers between Neural Network Engines and the Parallel Processing Unit, with SRAM as local storage | ||
* Neural Network Engine and Parallel Processing Unit synchronization with hardware semaphore | * Neural Network Engine and Parallel Processing Unit synchronization with hardware semaphore | ||
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[[Category:ORCA]] | [[Category:ORCA]] | ||
Latest revision as of 18:39, 28 December 2023
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| History | |||
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| 2021/02/04 | First release | ||
Peripheral NPU[edit | edit source]
The Neural Processign Unit (NPU) available on ORCA is based on iMX8MPlus SoC.
Description[edit | edit source]
The Neural Processing Unit (NPU) core accelerates vision image processing functions and provides enhanced performance for real-time use cases with hardware support for the OpenVX API.
Key features of the NPU block include:
- OpenVX 1.2 compliance, including extensions
- Convolutional Neural Network acceleration
- IEEE 32-bit floating-point pipeline in PPU shaders.
- Ultra-threaded parallel processing unit
- Low bandwidth at both high and low data rates
- Low CPU loading
- MMU functionality supported
- Performance Counters for DMA Profiling
- Data transfers between Neural Network Engines and the Parallel Processing Unit, with SRAM as local storage
- Neural Network Engine and Parallel Processing Unit synchronization with hardware semaphore
