Difference between revisions of "ORCA SOM/ORCA Hardware/Peripherals/NPU"
< ORCA SOM | ORCA Hardware
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| + | ==Peripheral NPU == | ||
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| + | {{Wip|text=Documentation under NXP's NDA: please refer to helpdesk@dave.eu }} | ||
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The Neural Processign Unit (NPU) available on ORCA is based on iMX8MPlus SoC. | The Neural Processign Unit (NPU) available on ORCA is based on iMX8MPlus SoC. | ||
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* Data transfers between Neural Network Engines and the Parallel Processing Unit, with SRAM as local storage | * Data transfers between Neural Network Engines and the Parallel Processing Unit, with SRAM as local storage | ||
* Neural Network Engine and Parallel Processing Unit synchronization with hardware semaphore | * Neural Network Engine and Parallel Processing Unit synchronization with hardware semaphore | ||
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[[Category:ORCA]] | [[Category:ORCA]] | ||
Revision as of 11:14, 5 March 2021
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| Version | Issue Date | Notes | |
| 1.0.0 | Feb 2021 | First release | |
Peripheral NPU[edit | edit source]
|
Documentation under NXP's NDA: please refer to helpdesk@dave.eu |
