Difference between revisions of "ORCA SOM/ORCA Hardware/Peripherals/LVDS"

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==Peripheral LVDS ==
 
==Peripheral LVDS ==
 
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The LVDS interface available on ORCA is based on iMX8MPlus SoC.
 
The LVDS interface available on ORCA is based on iMX8MPlus SoC.
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The Pin mapping is described in the [[ORCA SOM/ORCA Hardware/Pinout_Table | Pinout table section]]
 
The Pin mapping is described in the [[ORCA SOM/ORCA Hardware/Pinout_Table | Pinout table section]]
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[[Category:ORCA]]
 
[[Category:ORCA]]

Revision as of 15:32, 13 December 2021

History
Version Issue Date Notes
1.0.0 Feb 2021 First release


Peripheral LVDS[edit | edit source]

The LVDS interface available on ORCA is based on iMX8MPlus SoC.

This support covers all aspects of these activities:

  • Connectivity to relevant devices - Displays with LVDS receivers
  • Arranging the data as required by the external display receiver and by LVDS display standards
  • Synchronization and control capabilities

Description[edit | edit source]

The LVDS ports can be used as follows:

  • Single channel (4 lanes) output at up to 80MHz pixel clock and LVDS clock. This supports resolutions up to 1366x768p60.
  • Dual asynchronous channels (8 data, 2 clocks). This is intended for a single panel with two interfaces, transferring across two channels (even pixel/odd pixel). This is supported at up to 160MHz pixel clock, which is up to 80MHz LVDS clock (due to 2 pixels per LVDS clock). This supports resolutions above 1366x768p60, up to 1080p60.

Pin mapping[edit | edit source]

The Pin mapping is described in the Pinout table section