Difference between revisions of "MITO 8M SOM/MITO 8M Hardware/Peripherals/NAND"
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MITO 8M SOM provides a NAND interface available for an external memory device connection. | MITO 8M SOM provides a NAND interface available for an external memory device connection. | ||
| − | + | ||
| + | '''The availability of this interface is related to the SOM mounting option''': | ||
* on '''NAND on board''' version, the NAND interface is internally connected, and the SD1 interface is routed externally the SOM | * on '''NAND on board''' version, the NAND interface is internally connected, and the SD1 interface is routed externally the SOM | ||
* on '''eMMC on board''' version, the SD1 interface is internally connected, and the NAND interface is routed externally the SOM | * on '''eMMC on board''' version, the SD1 interface is internally connected, and the NAND interface is routed externally the SOM | ||
| − | See Pin mapping tables for connection details. | + | See Pin mapping tables for connection details. |
=== Description === | === Description === | ||
Revision as of 14:50, 7 October 2020
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Peripheral NAND[edit | edit source]
MITO 8M SOM provides a NAND interface available for an external memory device connection.
The availability of this interface is related to the SOM mounting option:
- on NAND on board version, the NAND interface is internally connected, and the SD1 interface is routed externally the SOM
- on eMMC on board version, the SD1 interface is internally connected, and the NAND interface is routed externally the SOM
See Pin mapping tables for connection details.
Description[edit | edit source]
The NAND interface available on MITO 8M is based on iMX8M SoC.
The NAND Flash controller supports the following standards and features:
- 8-bit NAND FLASH, up to 4 devices supported by 4 chip-selects and 1 ganged ready/busy
- ONFI 2.x complaint, synchronous clock rate of up to 100 MHz with data rate of up to 200 MB/s
- Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung
- BCH62 for ECC, up to 200MB/s
Pin mapping[edit | edit source]
The Pin mapping is described in the Pinout table section
