MISC-TN-027 — Qualifying a product for industrial, harsh environments: resilience against power supply anomalies

Info Box

History

Version	Date	Notes
1.0.0	July 2023	First public release

Introduction

Over the decades, DAVE Embedded Systems has been sharpening a tight qualification process for the products the company has been commissioned to design and manufacture. This process is relentlessly engineered to cope with the challenging requirements of the system-on-chips these products are based on and the industrial applications in harsh environments they drive.

This qualification process comprises several tests with different characteristics and goals. One of these tests is specifically designed for verifying the resilience of DUT's power supply unit (PSU) against supply voltage anomalies, which are pretty common in industrial environments. This Technical Note (TN for short) describes how we run this test.

Power supply anomalies resilience test

To make this test possible, DAVE Embedded Systems designed an ad hoc smart bench power supply denoted as PPSU. PPSU is used to power the DUT, which is the electronic device under test. You can think of PPSU as a programmable power waveform generator that is also able to verify the health status of the DUT. PPSU can generate an arbitrary supply voltage that exhibits purposely anomalies such as glitches and non-monotonic ramps. A robust product is expected to be resilient against these stressing conditions. In this context, by resilience we mean that either one of the following conditions occur:

• DUT is not affected at all and continues to operate regularly
• If it is inevitable that a hardware reset is triggered, DUT performs a warm reboot cycle and eventually returns to regular operating.

Of course, the expected behavior depends strongly on the nature and severity of injected anomalies. After an anomaly is injected, PPSU verifies whether the DUT is operating properly or not and logs the test result. PPSU can also be programmed to run the test cycle repeatedly for the desired number of iterations and optionally to stop if the test fails.

Combining several test waveforms of different types and running these tests over the entire DUT's operating temperature range allow to achieve good confidence that the product's PSU will not fail in the field because of "misbehaving" power supply. Furthermore, these tests are extremely useful to detect hardware design errors or more subtle situations like the one described in this application note by ST Microelectronics. Thank to the use of PPSU, during the qualification of the ETRA Single Board Computer, we had been able to spot the issue illustrated in this application note before STM released it publicly.

Hardware design

PPSU is implemented in the form of a single PCB that can operate in two modes:

• PPSUv2
• PPSUv3.

The following image shows the PPSU PCB. It integrates several sections whose purpose will be clear after illustrating the operating modes.

PPSUv2 is the legacy mode utilized when the PPSU board works in tandem with a PC. In this case, the PC hosts some programs required to "depict" the desired supply voltage. Once the waveform is defined, it is encoded in a proprietary format and sent to an FPGA that stores it in a RAM buffer. When the actual test starts, the logic implemented in the FPGA scans the waveform and feed a DAC. The analog signal output by the DAC is amplified by the power stage connected to the DUT.

PPSUv3 mode is an optimization of PPSUv2 mode. As depicted in the following image, in this case the PPSU board is connected to an embedded platform equipped with an FMC connector. For instance, BoraX/BoraXEVB system can be a viable system for this purpose. The advantage of using this approach is the fact that the system is much more compact. Also, it allows to implement advanced functionalities for controlling the DUT. For example, the analog inputs of Xilinx Zynq 7000 SoC can be used to measure some DUT's signals during the power cycles allowing to analyze in more detail its health status while testing progresses.

Examples

TBD