MISC-TN-003: Asymmetric multiprocessing on NXP i.MX6SoloX

History

Version	Date	Notes
1.0.0	November 2016	First public release

Introduction

Asymmetric multiprocessing (AMP for short) is getting popular in the embedded world, thanks to the availability of multi-core embedded processors. It is particularly useful tom combine in one single chip two different operating systems (o.s.). One of the most common combination is the use of a general purpose operating system (GPOS) with a real-time o.s. (RTOS), in order to meet both hard real-time constraints and generic connectivity/user interface requirements, with a highly integrated solution.

AMP can be implemented on homogeneous [1] and heterogeneous architectures. Either way, it poses significant challenges when it comes to handle resources that are unavoidably shared across different cores. ARM cores integrates TrustZone technology that can be exploited to face such issues, as described for example in this document.

Other system-on-chips (SOC) implements proprietary solution to handle the access to the shared resources. NXP i.MX6SoloX is an example of such components, as it integrates a so called Resource Domain Controller (RDC), that " provides robust support for the isolation of destination memory mapped locations such as peripherals and memory to a single core, a bus master, or set of cores and bus masters" as stated by the manufacturer [2].

This white paper describes an i.MX6UL-based AMP solution that has been implemented for a custom product.

[1] See for example this page.

[2] See NXP i.MX 6SoloX Applications Processor Reference Manual (IMX6SXRM).

Implementation

The following image shows in more detail the implementation of the solution.

caption

Is this case the role of the GPOS is played by Linux, while FreeRTOS has been used as RTOS. [1]

[1] For more details please refer to the FreeRTOS™ BSP for the i.MX 6SoloX ARM® Cortex®-M4 core.