Page history
2 May 2022
23 November 2021
→Traces length matching
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→Programmable logic (PL)
+189
→How to implement workaround suggested by Xilinx on BoraEVB
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28 October 2021
18 October 2019
U0007 moved page Integration guide (Bora/BoraX) to Integration guide (Bora/BoraX/BoraLite)
m→How to implement workaround suggested by Xilinx on BoraEVB
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no edit summary
+586
26 October 2017
5 October 2016
22 September 2016
25 March 2016
4 November 2015
U0001 moved page Integration guide (Bora) to Integration guide (Bora/BoraX)
mno edit summary
+21
→Programmable logic (PL)
+77
3 November 2015
31 August 2015
5 February 2015
→How to implement workaround suggested by Xilinx on BoraEVB
m+79
→How to implement workaround suggested by Xilinx on BoraEVB
m+2
→How to implement workaround suggested by Xilinx on BoraEVB
m+4
→PS' I²C buses
m+894
→PS' I²C buses
m+6
→PS' I²C buses
+1,534