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→Connecting the PUDC_B pin
On Bora SOM, PUDC_B pin is connected to FPGA_VDDIO_BANK34 (3.3V) via 10K resistor. This allows the external changes to the configuration of this pin, and the reusability of the same I/O pin after the configuration. In fact, PUDC_B pin can't be left floating before and during the configuration.
So it is OK to connect PUDC_B pin (J2 - Pin 15) to *'''P3V3_IOBANK* ''' via 1K pull-up resistor.
There are no side effects on BORA SOM putting I/O into high Z state.
